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gcc/
* common/config/riscv/riscv-common.cc (riscv_ext_version_table):
Add xcv and xcvhwlp.
(riscv_ext_flag_table): Likewise.
* config.gcc (riscv*): Add corev.o to extra_objs.
* config/riscv/constraints.md (xcvl0s, xcvl0e): New constraints.
(xcvl0c, xcvl1s, xcvl1e, xcvl1c): Likewise.
* config/riscv/corev.cc: New file.
* config/riscv/corev.md (UNSPEC_CV_LOOPBUG): New constant.
(doloop_end_i, *cv_start, *cv_end, *cv_count): New insn patterns.
(doloop_end, doloop_begin): New expanders.
(doloop_begin_i): New define_insn_and_split.
* config/riscv/predicates.md (lpstart_reg_op): New predicate.
(lpend_reg_op, lpcount_reg_op): Likewise.
(label_register_operand): Likewise.
* config/riscv/riscv-opts.h (MASK_XCVHWLP, TARGET_XCVHWLP): Define.
* config/riscv/riscv-passes.def (pass_riscv_doloop_begin): Add.
* config/riscv/riscv-protos.h (make_pass_riscv_doloop_begin): Declare.
(riscv_can_use_doloop_p, riscv_invalid_within_doloop): Likewise.
* hwloop_setupi_p, add_label_op_ref): Likewise.
* config/riscv/riscv.cc (riscv_regno_to_class): Add classes for
hardware loop start, end and counter registers.
(riscv_output_move): Add support to read loop counter registers.
(TARGET_CAN_USE_DOLOOP_P, TARGET_INVALID_WITHIN_DOLOOP): Override.
* config/riscv/riscv.h (enum reg_class): Add items for hardware
loop start, end and counter registers.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
(REG_ALLOC_ORDER): Likewise.
(REGISTER_NAMES): Likewise.
* config/riscv/riscv.md (LPSTART0_REGNUM): New constant.
(LPEND0_REGNUM, LPCOUNT0_REGNUM): Likewise.
(LPSTART1_REGNUM, LPEND1_REGNUM, LPCOUNT1_REGNUM): Likewise.
(attr ext): New value xcvhwlp.
(attr enabled): Handle xcvhwlp.
(movsi_internal): Add alternatives to read loop counters.
* config/riscv/t-riscv (corev.o): New rule.
* doc/md.texi (doloop_end): Document oprional operand 2.
* loop-doloop.cc (doloop_optimize): Provide 3rd operand to
gen_doloop_end.
* target-insns.def (doloop_end): Add optional 3rd operand.
gcc/testsuite/
* gcc.target/riscv/cv-hwlp-shiftsub.c: New test.