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Is this absolute hard limit->PCIe x1 (18 pins) generation 3.0 or above
#16
opened Aug 16, 2021 by
oiaohm
updated Aug 19, 2021
Refresh Time-Card repository
documentation
Improvements or additions to documentation
enhancement
New feature or request
#51
opened Mar 10, 2022 by
AlphaBetaPhi
updated Mar 10, 2022
Time in GPZDA on the NMEA serial port is incorrect
#70
opened Aug 9, 2022 by
MaciekMachni
updated Aug 10, 2022
Some questions about MAC and Address mapped
#66
opened Jul 21, 2022 by
Satoshier
updated Jan 26, 2023
ptp_ocp on RPi CM4 doesn't expose NMEA TTY and GNSS TTY
#73
opened Aug 12, 2022 by
MaciekMachni
updated Jan 27, 2023
Production Timecard: mismatch between board and FPGA PCIe lane counts
#92
opened Mar 7, 2023 by
wisxxx
updated Mar 8, 2023
SA45 osc daughtercard does not bring out LOCK signal
#88
opened Feb 2, 2023 by
wisxxx
updated Aug 9, 2023
LOF (ver 0.1) mechanical drawing is incomplete
#87
opened Jan 30, 2023 by
wisxxx
updated Aug 9, 2023
TimeCard starts with a random frequency offset on 10 MHz output
#74
opened Aug 22, 2022 by
MaciekMachni
updated Aug 9, 2023
Is GNSS dependance the mistake? Should part of this include back to basics. Solar/moon calibration.
#69
opened Aug 1, 2022 by
oiaohm
updated Aug 9, 2023
Production Timecard: bad termination on FPGA JTAG with USB
#90
opened Mar 1, 2023 by
wisxxx
updated Aug 9, 2023
Time Card PCB queries from PCBway regarding vias in pad.
#96
opened Jul 28, 2023 by
ghost
updated Oct 31, 2023
Should the version numbers in the CoreList be the same as the version registers?
#104
opened Nov 18, 2023 by
JohnHay
updated Nov 23, 2023
Connecting 1PPS and 10MHz outputs with 50 Ohm termination to another TimeCard 1PPS and 10MHz inputs
#105
opened Mar 15, 2024 by
vlvassilev
updated Mar 15, 2024
OCXO Daughter Card V4 - Silkscreen Designator Mismatch for R8 and R33
#107
opened May 23, 2024 by
skear
updated May 23, 2024
R6 Placement Interferes with Y3 (Abracon AOCJYR) on OCXO Daughter Card
#108
opened May 29, 2024 by
skear
updated May 29, 2024
ProTip!
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