RISC-V Profiles and Platform Specification

cloc counts blank lines, comment lines, and physical lines of source code in many programming languages.

🌟 Wiki of OI / ICPC for everyone. （某大型游戏线上攻略，内含炫酷算术魔法）

Rocket Chip Generator

Grok open release

Chisel: A Modern Hardware Design Language

Flexible Intermediate Representation for RTL

chisel tutorial exercises and answers

Generator Bootcamp Material: Learn Chisel the Right Way

AI Infra主要是指AI的基础建设，包括AI芯片、AI编译器、AI推理和训练框架等AI全栈底层技术。

AISystem 主要是指AI系统，包括AI芯片、AI编译器、AI推理和训练框架等AI全栈底层技术

GNU Libc - Extremely old repo used for research purposes years ago. Please do not rely on this repo.

Stable Diffusion web UI

Python package for writing Value Change Dump (VCD) files.

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Protocol Buffers - Google's data interchange format

'Classic' FreeRTOS distribution. Started as Git clone of FreeRTOS SourceForge SVN repo. Submodules the kernel.

TensorFlow's Visualization Toolkit

fitlog是一款在深度学习训练中用于辅助用户记录日志和管理代码的工具

The AI developer platform. Use Weights & Biases to train and fine-tune models, and manage models from experimentation to production.

Linux命令大全搜索工具，内容包含Linux命令手册、详解、学习、搜集。https://git.io/linux

Third party firmware for Asus routers (newer codebase)

Automated Redpill Loader

Spike, a RISC-V ISA Simulator

PLIC Specification

A fast JSON parser/generator for C++ with both SAX/DOM style API

Study parallel programming - CUDA, OpenMP, MPI, Pthread

A FPGA friendly 32 bit RISC-V CPU implementation