Backport changes made to nrf52-hal after split

boards/adafruit_nrf52pro/src/lib.rs

@@ -5,22 +5,22 @@ pub use hal::nrf52;
 
 /// Maps the pins to the names printed on the device
 pub struct Pins {
-    pub a0: p0::P0_2<Input<Floating>>,
-    pub a1: p0::P0_3<Input<Floating>>,
-    pub a2: p0::P0_4<Input<Floating>>,
-    pub a3: p0::P0_5<Input<Floating>>,
+    pub a0: p0::P0_02<Input<Floating>>,
+    pub a1: p0::P0_03<Input<Floating>>,
+    pub a2: p0::P0_04<Input<Floating>>,
+    pub a3: p0::P0_05<Input<Floating>>,
     pub a4: p0::P0_28<Input<Floating>>,
     pub a5: p0::P0_29<Input<Floating>>,
     pub sck: p0::P0_12<Input<Floating>>,
     pub mosi: p0::P0_13<Input<Floating>>,
     pub miso: p0::P0_14<Input<Floating>>,
-    pub txd: p0::P0_8<Input<Floating>>,
-    pub rxd: p0::P0_6<Input<Floating>>,
+    pub txd: p0::P0_08<Input<Floating>>,
+    pub rxd: p0::P0_06<Input<Floating>>,
     pub dfu: p0::P0_20<Input<Floating>>,
     pub frst: p0::P0_22<Input<Floating>>,
     pub d16: p0::P0_16<Input<Floating>>,
     pub d15: p0::P0_15<Input<Floating>>,
-    pub d7: p0::P0_7<Input<Floating>>,
+    pub d7: p0::P0_07<Input<Floating>>,
     pub d11: p0::P0_11<Input<Floating>>,
     pub a7: p0::P0_31<Input<Floating>>,
     pub a6: p0::P0_30<Input<Floating>>,
@@ -34,22 +34,22 @@ pub struct Pins {
 impl Pins {
     pub fn new(pins: p0::Parts) -> Self {
         Self {
-            a0: pins.p0_2,
-            a1: pins.p0_3,
-            a2: pins.p0_4,
-            a3: pins.p0_5,
+            a0: pins.p0_02,
+            a1: pins.p0_03,
+            a2: pins.p0_04,
+            a3: pins.p0_05,
             a4: pins.p0_28,
             a5: pins.p0_29,
             sck: pins.p0_12,
             mosi: pins.p0_13,
             miso: pins.p0_14,
-            txd: pins.p0_8,
-            rxd: pins.p0_6,
+            txd: pins.p0_08,
+            rxd: pins.p0_06,
             dfu: pins.p0_20,
             frst: pins.p0_22,
             d16: pins.p0_16,
             d15: pins.p0_15,
-            d7: pins.p0_7,
+            d7: pins.p0_07,
             d11: pins.p0_11,
             a7: pins.p0_31,
             a6: pins.p0_30,

nrf52-hal-common/src/gpio.rs

@@ -283,16 +283,16 @@ macro_rules! gpio {
 // 32-bit GPIO port (P0)
 // ===========================================================================
 gpio!(P0, p0, P0_Pin [
-    P0_0:  (p0_0,  0,  Input<Floating>),
-    P0_1:  (p0_1,  1,  Input<Floating>),
-    P0_2:  (p0_2,  2,  Input<Floating>),
-    P0_3:  (p0_3,  3,  Input<Floating>),
-    P0_4:  (p0_4,  4,  Input<Floating>),
-    P0_5:  (p0_5,  5,  Input<Floating>),
-    P0_6:  (p0_6,  6,  Input<Floating>),
-    P0_7:  (p0_7,  7,  Input<Floating>),
-    P0_8:  (p0_8,  8,  Input<Floating>),
-    P0_9:  (p0_9,  9,  Input<Floating>),
+    P0_00: (p0_00,  0, Input<Floating>),
+    P0_01: (p0_01,  1, Input<Floating>),
+    P0_02: (p0_02,  2, Input<Floating>),
+    P0_03: (p0_03,  3, Input<Floating>),
+    P0_04: (p0_04,  4, Input<Floating>),
+    P0_05: (p0_05,  5, Input<Floating>),
+    P0_06: (p0_06,  6, Input<Floating>),
+    P0_07: (p0_07,  7, Input<Floating>),
+    P0_08: (p0_08,  8, Input<Floating>),
+    P0_09: (p0_09,  9, Input<Floating>),
     P0_10: (p0_10, 10, Input<Floating>),
     P0_11: (p0_11, 11, Input<Floating>),
     P0_12: (p0_12, 12, Input<Floating>),

nrf52-hal-common/src/spim.rs

@@ -191,6 +191,77 @@ impl<T> Spim<T> where T: SpimExt {
         Ok(())
     }
 
+    /// Write to an SPI slave
+    ///
+    /// This method uses the provided chip select pin to initiate the
+    /// transaction, then transmits all bytes in `tx_buffer`.
+    ///
+    /// The buffer must have a length of at most 255 bytes.
+    pub fn write(&mut self,
+        chip_select: &mut P0_Pin<Output<PushPull>>,
+        tx_buffer  : &[u8],
+    )
+        -> Result<(), Error>
+    {
+        // This is overly restrictive. See:
+        // https://github.com/nrf-rs/nrf52/issues/17
+        if tx_buffer.len() > u8::max_value() as usize {
+            return Err(Error::TxBufferTooLong);
+        }
+
+        // Pull chip select pin high, which is the inactive state
+        chip_select.set_high();
+
+        // Set up the DMA write
+        self.0.txd.ptr.write(|w|
+            // We're giving the register a pointer to the stack. Since we're
+            // waiting for the SPI transaction to end before this stack pointer
+            // becomes invalid, there's nothing wrong here.
+            //
+            // The PTR field is a full 32 bits wide and accepts the full range
+            // of values.
+            unsafe { w.ptr().bits(tx_buffer.as_ptr() as u32) }
+        );
+        self.0.txd.maxcnt.write(|w|
+            // We're giving it the length of the buffer, so no danger of
+            // accessing invalid memory. We have verified that the length of the
+            // buffer fits in an `u8`, so the cast to `u8` is also fine.
+            //
+            // The MAXCNT field is 8 bits wide and accepts the full range of
+            // values.
+            unsafe { w.maxcnt().bits(tx_buffer.len() as _) }
+        );
+
+        // Tell the RXD channel it doesn't need to read anything
+        self.0.rxd.maxcnt.write(|w|
+            // This is safe for the same reasons that writing to TXD.MAXCNT is
+            // safe. Please refer to the explanation there.
+            unsafe { w.maxcnt().bits(0) }
+        );
+
+        // Start SPI transaction
+        chip_select.set_low();
+        self.0.tasks_start.write(|w|
+            // `1` is a valid value to write to task registers.
+            unsafe { w.bits(1) }
+        );
+
+        // Wait for transmission to end
+        while self.0.events_end.read().bits() == 0 {}
+
+        // Reset the event, otherwise it will always read `1` from now on.
+        self.0.events_end.write(|w| w);
+
+        // End SPI transaction
+        chip_select.set_high();
+
+        if self.0.txd.amount.read().bits() != tx_buffer.len() as u32 {
+            return Err(Error::Transmit);
+        }
+
+        Ok(())
+    }
+
     /// Return the raw interface to the underlying SPIM peripheral
     pub fn free(self) -> T {
         self.0