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@colltoaction
Martin Coll colltoaction
Let's rethink computing

🇦🇷

@superfpga
supergtr superfpga
Digital Design Senior Architecture Engineer !!!

AVIC Beijing China

@iDoka
Dmitry Murzinov iDoka
Hardware Imagineer | Digital IC Design Engineer | Automotive Electronics Enthusiast

@dokard @deepware-ai Error: Unable to resolve

@djoffe
Daniel Joffe djoffe

Lausanne, Switzerland

@kaoruzhu1
kaoruzhu1
Absolute Novice

NONE WuHan, China

@yuravg
Yuriy Gritsenko yuravg
FPGA Design Engineer

RF, Saint-Petersburg

@Hello-FPGA
Hello-FPGA Hello-FPGA

Hello-FPGA chongqing

@jerralph
Jeremy Ralph jerralph
Computer Engineering. 20+ years of experience in Chip Design/Verification, Software and Firmware Development.

bigco Vancouver Island

@hjking
HJKing hjking
ASIC Verification Engineer in China. A Vim, Emacs and Linux user.

Wuhan, China

@troyguo
troyguo
IC Verification, Linux Kernel.

Shanghai, China

@shady831213
Apollo Li shady831213
Just for fun!

Picocom Beijing

@ronilazzari
Ronì Lazzari ronilazzari
A pile of failures and regrets who crafts code and hardware to (try to) feel less miserable, and more creative. And sometimes I am too dramatic.

CEITEC Porto Alegre

@ypersyntelykos
ypersyntelykos ypersyntelykos
Twitter : @ypersyntelykos Linkedin : https://www.linkedin.com/in/ypersyntelykos/

Athens, Greece

@ciroceissler
Ciro Luiz Araujo Ceissler ciroceissler
ASIC Verification Engineer

Renesas Munich - Germany

@tudortimi
Tudor Timi tudortimi
Verification Engineer by day, Verification Gentleman by night.

Verification Gentleman

@mramdas
Ramdas M mramdas
-Experienced Verification Engineer, Online teacher -Author of "Cracking Digital VLSI Verification Interview : Interview Success -Quora blogger

Verification Excellence Online

@mplavcan
Matt Plavcan mplavcan
Hardware/software developer, Technical practices coach

Tacit Focus, LLC Portland, OR

@dpretet
Damien Pretet dpretet
FPGA/ASIC Design Engineer

France