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nishit0072e/README.md

Hi 👋, I'm Nishit Bayen

A passionate HW/FW developer from India

new

nishit0072e

  • 🔭 I’m currently working on ASIC Design Flow

  • 🌱 I’m currently learning Hardware Design, Firmware Development

  • 👯 I’m looking to collaborate on VLSI Projects

Connect with me:

nishit-bayen-🇮🇳-423aa421b nishit bayen _nix0072e_ nishitbayen2021

Languages and Tools:

arduino blender c firebase git ifttt linux matlab opencv python

nishit0072e

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  1. sev_seg_FPGA sev_seg_FPGA Public

    its a seven segment display controller in FPGA which counts in ascending order

    JavaScript

  2. 100DaysOfRtlDesign 100DaysOfRtlDesign Public

    Forked from ShashankSirohiya/100DaysOfRtl

    I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.

    Verilog 1

  3. Enc_Dec_Xor Enc_Dec_Xor Public

    8:3 Encoder is used as input and 3:8 decoder is used as output, to verify that the input and output data are same a Xor gate is implemented, it will return 1 if any mismatch in the input and output…

    Verilog

  4. WIFI_CAR WIFI_CAR Public

    A code to operate a battery operated car over wifi control

    C++