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Software Engineering Lab, SFU
- Vancouver, BC
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21:02
(UTC -07:00) - in/nimamg
Highlights
- Pro
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DynaPyt Public
Forked from sola-st/DynaPytDynamic analysis framework for Python
Python MIT License UpdatedOct 17, 2024 -
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saga-undergrad-project Public
Simple modelling of three microservices using Python classes
Python UpdatedJul 10, 2022 -
documentation Public
Forked from coreruleset/documentationCRS Documentation
JavaScript UpdatedJan 14, 2022 -
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Huffmann-Caesar Public
Given a text file, this code can compress, encrypt, decrypt, decompress and hash the file
C++ UpdatedJun 9, 2019 -
MIPS-Pipeline Public
A pipeline implementation of the MIPS processor
SystemVerilog UpdatedMay 31, 2019 -
Business-social-network Public
A business-based social network, loosely based on LinkedIn, No GUI
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Regex-validation Public
A simple code trying to validate a string based on a regex (in simple manners)
C++ UpdatedMay 16, 2019 -
Heartbeat-measurement Public
Measuring a person's heartbeat using a video of his/her fingertip on a camera lens
MATLAB UpdatedMay 16, 2019 -
MultiCycle-CPU Public
A multi cycle CPU based on MIPS architecture
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ContactBin-AP-CA1 Public
A contact bin, developed as the solution to the first assignment of the Advanced Programming course at the University of Tehran. Sorry for bad code style :)) it was developed a long time ago and it…
C++ UpdatedMay 9, 2019 -
JeekJeek Public
Tried to replicate Twitter in simple manners with a simple HTML GUI as part of the assingments for the Advanced Programming course
C++ UpdatedMay 9, 2019 -
ContactBin-Refactored Public
ContactBin (https://github.com/nmgtav/ContactBin-AP-CA1) refactored.
C++ UpdatedMay 9, 2019 -
SingleCycle-CPU Public
A single cycle CPU, simulated using Verilog
SystemVerilog UpdatedMay 9, 2019 -
Perceptron-node Public
A perceptron node implementation using verilog
SystemVerilog UpdatedMay 9, 2019 -
UT-DLD-Tangent-Calculator Public
A tangent calculator written in Verilog; Datapath designed by Quartus II and controller was coded in verilog.
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UT-DLD-FrequencyMultiplier Public
A frequency multiplier built using RTL components and design.
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UT-DLD-Counters-Registers Public
An n-bit counter with 4 functionality modes & many different registers (latches and FlipFlops)
Verilog UpdatedMay 5, 2019 -
UT-DLD-One-s-Counter Public
Building 7, 15 and 127 bit one's counters using full adders
Verilog UpdatedMay 5, 2019 -
DLD-Full-Adder Public
Built a Full Adder (One counter) using switch-level coding, gate-level coding, and assign commands
Verilog UpdatedMay 5, 2019