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  • Software Engineering Lab, SFU
  • Vancouver, BC
  • 21:02 (UTC -07:00)
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  • DynaPyt Public

    Forked from sola-st/DynaPyt

    Dynamic analysis framework for Python

    Python MIT License Updated Oct 17, 2024
  • Python 2 Updated Sep 4, 2024
  • Simple modelling of three microservices using Python classes

    Python Updated Jul 10, 2022
  • CRS Documentation

    JavaScript Updated Jan 14, 2022
  • SAD-Phase4 Public

    JavaScript Updated Sep 22, 2021
  • HTML Updated Aug 29, 2021
  • xv6 OS

    C Other Updated May 6, 2021
  • C++ 1 Updated Jul 20, 2020
  • SystemVerilog 1 1 Updated Jun 18, 2019
  • Implementing the Droste effect on a picture

    Python Updated Jun 14, 2019
  • A simple game made by unity

    C# Updated Jun 14, 2019
  • Given a text file, this code can compress, encrypt, decrypt, decompress and hash the file

    C++ Updated Jun 9, 2019
  • A pipeline implementation of the MIPS processor

    SystemVerilog Updated May 31, 2019
  • A business-based social network, loosely based on LinkedIn, No GUI

    C++ 1 Updated May 24, 2019
  • A simple code trying to validate a string based on a regex (in simple manners)

    C++ Updated May 16, 2019
  • Measuring a person's heartbeat using a video of his/her fingertip on a camera lens

    MATLAB Updated May 16, 2019
  • A multi cycle CPU based on MIPS architecture

    SystemVerilog 1 Updated May 12, 2019
  • A contact bin, developed as the solution to the first assignment of the Advanced Programming course at the University of Tehran. Sorry for bad code style :)) it was developed a long time ago and it…

    C++ Updated May 9, 2019
  • JeekJeek Public

    Tried to replicate Twitter in simple manners with a simple HTML GUI as part of the assingments for the Advanced Programming course

    C++ Updated May 9, 2019
  • ContactBin (https://github.com/nmgtav/ContactBin-AP-CA1) refactored.

    C++ Updated May 9, 2019
  • A single cycle CPU, simulated using Verilog

    SystemVerilog Updated May 9, 2019
  • A perceptron node implementation using verilog

    SystemVerilog Updated May 9, 2019
  • A tangent calculator written in Verilog; Datapath designed by Quartus II and controller was coded in verilog.

    Verilog 3 Updated May 5, 2019
  • A frequency multiplier built using RTL components and design.

    Verilog 1 Updated May 5, 2019
  • An n-bit counter with 4 functionality modes & many different registers (latches and FlipFlops)

    Verilog Updated May 5, 2019
  • Building 7, 15 and 127 bit one's counters using full adders

    Verilog Updated May 5, 2019
  • Built a Full Adder (One counter) using switch-level coding, gate-level coding, and assign commands

    Verilog Updated May 5, 2019