detect risc-v zfbfmin and zicond extension

[dtcxzyw]

This patch adds support for RISC-V zfbfmin: Scalar BF16 converts and zicond: Integer Conditional Operations.

Machine code is generated by llvm toolchain:

// llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zfbfmin,+zicond < tmp.S | llvm-objdump --mattr=+experimental-zfbfmin,+zicond -d -r -
add a0,a0,a0
fcvt.bf16.s ft0,ft0
czero.eqz a0,a0,a0

<stdin>:        file format elf64-littleriscv

Disassembly of section .text:

0000000000000000 <.text>:
       0: 33 05 a5 00   add     a0, a0, a0
       4: 53 70 80 44   fcvt.bf16.s     ft0, ft0
       8: 33 55 a5 0e   czero.eqz       a0, a0, a0

Tested with qemu 9.0.50 (v9.0.0-519-ge116b92d01)

riscv64-linux-gnu-gcc main.c
qemu-riscv64 -L /usr/riscv64-linux-gnu/ -cpu rv64,zfbfmin=false ./a.out | grep "zfbfmin = 0"
qemu-riscv64 -L /usr/riscv64-linux-gnu/ -cpu rv64,zfbfmin=true ./a.out | grep "zfbfmin = 1"
qemu-riscv64 -L /usr/riscv64-linux-gnu/ -cpu rv64,zicond=false ./a.out | grep "zicond = 0"
qemu-riscv64 -L /usr/riscv64-linux-gnu/ -cpu rv64,zicond=true ./a.out | grep "zicond = 1"

[nihui]

Thanks for your contribution !