Skip to content
View nekrasov-d's full-sized avatar
4 followers · 2 following
  • Moscow, Russia
Block or Report

Block or report nekrasov-d

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. gabella gabella Public

    Audio processor based on FPGA (real hardware project)

    SystemVerilog 1

  2. digital-filters digital-filters Public

    RTL (Verilog) digital filter library based on Python scipy library output (mostly)

    SystemVerilog

  3. dsp-testbench-template dsp-testbench-template Public

    A Python-SystemVerilog testbench template for standard interface DSP module veirfication

    SystemVerilog

  4. sdft sdft Public

    Sliding window discrete Fourier transform SystemVerilog core

    SystemVerilog

  5. cordic-based-math cordic-based-math Public

    RTL (SystemVerilog) libraty of arithmetic modules based on CORDIC algorithm

    SystemVerilog