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1. chipyard chipyard Public

   Forked from ucb-bar/chipyard

   An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

   Scala 1 1

2. BURQ-single-cyclic-core-RISC-V BURQ-single-cyclic-core-RISC-V Public

   Forked from rawheel/BURQ-single-cyclic-core-RISC-V

   This is the single cyclic core based on RISC-V ISA code is in chisel language which is a module of Scala language.e

   TeX

3. 5-stage-pipeline-RISC-V_ISA 5-stage-pipeline-RISC-V_ISA Public

   Forked from rawheel/5-stage-pipeline-core-RISC-V_ISA

   This repository contains 5 stage pipeline core on RISC-V ISA.

   TeX

4. Hamming-ECC Hamming-ECC Public

   Forked from RoaLogic/Hamming-ECC

   Hamming ECC Encoder and Decoder to protect memories

   SystemVerilog

5. RV12 RV12 Public

   Forked from RoaLogic/RV12

   RISC-V CPU Core

   SystemVerilog

6. scala_sample scala_sample Public

   configuring scala with eclipse

   Scala