Checking SystemVerilog IEEE-2023 and IEEE-2017 synthesis capabilities.

UserspaceIO helper library

Sample of project using UIO(User Space IO) Interrupt(ZYBO/Linux/PUMP_AXI4).

Kactus2 is a graphical EDA tool based on the IP-XACT standard.

memtool is a program that allows to access memory mapped registers.

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Github Copilot-like LSP code completion server with local LLM powered by llama.cpp

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Control and status register code generator toolchain

D3.js and ELK based schematic visualizer

Web-based HDL diagramming tool

💡 Digital Circuit rendering engine

Determines the modules declared and instantiated in a SystemVerilog file

modify netlistsvg to show the information of each modules

A list of resources related to the open-source FPGA projects

A Symbolic Package for Octave using SymPy

A git-friendly Vivado wrapper

🧛🏻‍♂️ Dark theme for Vivado

Lightweight C++ command line option parser

This is a tutorial to install ubuntu 20.4 in an external HDD without removing the internal HDD in windows.

Easy access to gitignore boilerplates

Dark theme for doxygen documentation generator

Apply and save color schemes in MATLAB with ease.

Make function keys default on Logitech k380 bluetooth keyboard