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RTL-language-BSV-BSV_Tutorial_cn
RTL-language-BSV-BSV_Tutorial_cn PublicForked from WangXuan95/BSV_Tutorial_cn
爆肝6万字的 Bluespec SystemVerilog (BSV) 中文教程
Bluespec
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RTL-tools-vim-verilog_systemverilog.vim
RTL-tools-vim-verilog_systemverilog.vim PublicForked from vhda/verilog_systemverilog.vim
Verilog/SystemVerilog Syntax and Omni-completion
Vim Script
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RTL-design-riscv-e203_hbirdv2
RTL-design-riscv-e203_hbirdv2 PublicForked from riscv-mcu/e203_hbirdv2
The Ultra-Low Power RISC-V Core
Verilog
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RTL-tools-language-bsc
RTL-tools-language-bsc PublicForked from B-Lang-org/bsc
Bluespec Compiler (BSC)
Haskell
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RTL-design-RISCV-BSV-refer-Flute
RTL-design-RISCV-BSV-refer-Flute PublicForked from bluespec/Flute
RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
Bluespec
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