Gephi - The Open Graph Viz Platform

Source Code for training and evaluating BranchNet models for branch prediction

SonicBOOM: The Berkeley Out-of-Order Machine

A SystemVerilog Language Server

Working Draft of the RISC-V Debug Specification Standard

Educational Operating System

Build and run scripts for MikanOS

Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, T…

RISC-V Proxy Kernel

Lemonade is a remote utility tool. (copy, paste and open browser) over TCP.

Spike, a RISC-V ISA Simulator

Powerful yet simple to use screenshot software 🖥️ 📸

⚡ Automates terminal operations.

ChampSim is an open-source trace based simulator maintained at Texas A&M University and through the support of the computer architecture community.

Xv6 for RISC-V

Simple Python interface for Graphviz

Veryl: A Modern Hardware Description Language

SystemVerilog parser library fully compliant with IEEE 1800-2017

Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.

A fast and easy-to-use status bar

A huge collection of Rofi based custom Applets, Launchers & Powermenus.

CPU assembly examples

Icon and filename column for ddu.vim

API Documentation Browser

Pandoc filter for cross-references

Universal markup converter