removed one additional waiting cycle when using zero padding

This was achieved by restructuring the zero padding module slightly.
marph91 · Nov 1, 2020 · bff41b7 · bff41b7
1 parent 10bbdd3
commit bff41b7
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Showing 3 changed files with 3 additions and 10 deletions.
diff --git a/code/vhdl/sim/vunit/top/src/tb_top.vhd b/code/vhdl/sim/vunit/top/src/tb_top.vhd
@@ -235,9 +235,6 @@ begin
  wait until rising_edge(sl_clk);
  end loop;
  sl_valid_in <= '0';
- -- one more waiting cycle, because else padding would accept too much input data
- -- TODO: fix it (send data as long as sl_rdy = '1')
- wait until rising_edge(sl_clk);
  end if;
  end loop;
  end loop;

diff --git a/code/vhdl/sim/vunit/zero_pad/src/tb_zero_pad.vhd b/code/vhdl/sim/vunit/zero_pad/src/tb_zero_pad.vhd
@@ -118,7 +118,6 @@ begin
  i := i + 1;
  end loop;
  sl_valid_in <= '0';
- wait until rising_edge(sl_clk);
  end loop;
 
  stimuli_done <= true;

diff --git a/code/vhdl/src/zero_pad.vhd b/code/vhdl/src/zero_pad.vhd
@@ -41,7 +41,6 @@ architecture behavioral of zero_pad is
 
  signal sl_output_valid : std_logic := '0';
  signal slv_data_out : std_logic_vector(C_DATA_WIDTH - 1 downto 0);
- signal sl_rdy : std_logic := '0';
 
  type t_states is (IDLE, PAD, PAD_PIXEL, FORWARD_DATA);
 
@@ -93,7 +92,6 @@ begin
  case state is
 
  when IDLE =>
- sl_rdy <= '0';
  if (int_pixel_to_pad > 0) then
  state <= PAD;
  end if;
@@ -120,12 +118,10 @@ begin
  end if;
 
  when FORWARD_DATA =>
- sl_rdy <= '1';
  slv_data_out <= islv_data;
  sl_output_valid <= isl_valid;
  if (int_pixel_to_pad > 0) then
- state <= PAD;
- sl_rdy <= '0';
+ state <= PAD;
  end if;
 
  end case;
@@ -136,6 +132,7 @@ begin
 
  osl_valid <= sl_output_valid;
  oslv_data <= slv_data_out;
- osl_rdy <= sl_rdy and isl_get;
+ osl_rdy <= isl_get when (state = FORWARD_DATA and int_pixel_to_pad = 0) else
+ '0';
 
 end architecture behavioral;