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added the common counters to more modules
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Also reworked the zero padding slightly.
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@marph91
marph91 committed Dec 23, 2020
1 parent 991f434 commit 4ab8023
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Showing 4 changed files with 135 additions and 112 deletions.
88 changes: 47 additions & 41 deletions code/vhdl/src/conv.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -66,13 +66,39 @@ architecture behavioral of conv is
signal slv_bias : std_logic_vector(C_WEIGHTS_TOTAL_BITS - 1 downto 0);

-- debug
signal int_ch_in_cnt : integer := 0;
signal int_pixel_in_cnt : integer := 0;
signal int_ch_out_cnt : integer range 0 to C_CH_OUT - 1 := 0;
signal int_pixel_out_cnt : integer := 0;
signal int_ch_in_cnt : integer range 0 to C_CH_IN - 1 := 0;
signal int_ch_out_cnt : integer range 0 to C_CH_OUT - 1 := 0;

begin

-- synthesis translate off
i_pixel_counter_in : entity util.basic_counter
generic map (
C_MAX => C_CH_IN,
C_INCREMENT => C_PARALLEL_CH
)
port map (
isl_clk => isl_clk,
isl_reset => '0',
isl_valid => isl_valid,
oint_count => int_ch_in_cnt,
osl_maximum => open
);

i_pixel_counter_out : entity util.basic_counter
generic map (
C_MAX => C_CH_OUT
)
port map (
isl_clk => isl_clk,
isl_reset => '0',
isl_valid => osl_valid,
oint_count => int_ch_out_cnt,
osl_maximum => open
);

-- synthesis translate on

gen_mm : for ch_in in 0 to C_PARALLEL_CH - 1 generate
i_mm : entity work.mm
generic map (
Expand All @@ -96,30 +122,23 @@ begin

end generate gen_mm;

proc_cnt : process (isl_clk) is
begin

if (rising_edge(isl_clk)) then
if (isl_valid = '1') then
if (int_ch_in_cnt < C_CH_IN * C_CH_OUT - C_PARALLEL_CH) then
int_ch_in_cnt <= int_ch_in_cnt + C_PARALLEL_CH;
else
int_ch_in_cnt <= 0;
int_pixel_in_cnt <= int_pixel_in_cnt + 1;
end if;
end if;

if (sl_valid_out = '1') then
if (int_ch_out_cnt < C_CH_OUT - 1) then
int_ch_out_cnt <= int_ch_out_cnt + 1;
else
int_ch_out_cnt <= 0;
int_pixel_out_cnt <= int_pixel_out_cnt + 1;
end if;
end if;
end if;

end process proc_cnt;
i_address_counter : entity util.pixel_counter(single_process)
generic map (
C_HEIGHT => 1,
-- bias addresses depend on output channel
C_WIDTH => C_CH_OUT,
C_CHANNEL => C_CH_IN,
C_CHANNEL_INCREMENT => C_PARALLEL_CH
)
port map (
isl_clk => isl_clk,
isl_reset => '0',
isl_valid => sl_mm_valid_out(0),
oint_pixel => int_addr_cnt_b,
oint_row => open,
oint_column => open,
oint_channel => int_mm_out_cnt
);

proc_data : process (isl_clk) is

Expand All @@ -131,19 +150,6 @@ begin
sl_mm_valid_out_d1 <= sl_mm_valid_out(0);

if (sl_mm_valid_out(0) = '1') then
if (int_mm_out_cnt < C_CH_IN - C_PARALLEL_CH) then
int_mm_out_cnt <= int_mm_out_cnt + C_PARALLEL_CH;
else
int_mm_out_cnt <= 0;

-- bias addresses depend on output channel
if (int_addr_cnt_b < C_CH_OUT - 1) then
int_addr_cnt_b <= int_addr_cnt_b + 1;
else
int_addr_cnt_b <= 0;
end if;
end if;

-- assign the first value (bias)
if (int_mm_out_cnt = 0) then
v_sfix_sum := resize(to_sfixed(C_BIAS(int_addr_cnt_b)(0, 0),
Expand Down
52 changes: 19 additions & 33 deletions code/vhdl/src/pe.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -80,39 +80,25 @@ architecture behavioral of pe is

begin

proc_cnt : process (isl_clk) is
begin

if (rising_edge(isl_clk)) then
if (isl_start = '1') then
-- have to be resetted at start because of odd kernels (3x3+2) -> image dimensions arent fitting kernel stride
int_pixel_in_cnt <= 0;
int_ch_in_cnt <= 0;
int_col <= 0;
int_row <= 0;
else
if (isl_valid = '1') then
if (int_ch_in_cnt < C_CH_IN - 1) then
int_ch_in_cnt <= int_ch_in_cnt + 1;
else
int_ch_in_cnt <= 0;
int_pixel_in_cnt <= int_pixel_in_cnt + 1;
if (int_col < C_IMG_WIDTH - 1) then
int_col <= int_col + 1;
else
int_col <= 0;
if (int_row < C_IMG_HEIGHT - 1) then
int_row <= int_row + 1;
else
int_row <= 0;
end if;
end if;
end if;
end if;
end if;
end if;

end process proc_cnt;
-- synthesis translate off
i_pixel_counter : entity util.pixel_counter(single_process)
generic map (
C_HEIGHT => C_IMG_HEIGHT,
C_WIDTH => C_IMG_WIDTH,
C_CHANNEL => C_CH_IN,
C_CHANNEL_INCREMENT => C_PARALLEL_CH
)
port map (
isl_clk => isl_clk,
isl_reset => isl_start,
isl_valid => isl_valid,
oint_pixel => int_pixel_in_cnt,
oint_row => int_row,
oint_column => int_col,
oint_channel => int_ch_in_cnt
);

-- synthesis translate on

-- zero padding

Expand Down
6 changes: 4 additions & 2 deletions code/vhdl/src/window_ctrl/window_ctrl.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -189,7 +189,7 @@ begin
oint_channel => open
);

-- only for debugging
-- synthesis translate off
i_pixel_counter_out : entity util.pixel_counter(single_process)
generic map (
C_HEIGHT => 1,
Expand All @@ -199,13 +199,15 @@ begin
port map (
isl_clk => isl_clk,
isl_reset => isl_start,
isl_valid => osl_valid,
isl_valid => sl_repeater_valid_out,
oint_pixel => open,
oint_row => open,
oint_column => open,
oint_channel => open
);

-- synthesis translate on

oslv_data <= array_to_slv(a_repeater_data_out);
osl_valid <= sl_repeater_valid_out;
-- Use isl_valid, sl_lb_valid_out and sl_wb_valid_out to get three less cycles of the ready signal.
Expand Down
101 changes: 65 additions & 36 deletions code/vhdl/src/zero_pad.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,8 @@
library ieee;
use ieee.std_logic_1164.all;

library util;

entity zero_pad is
generic (
C_DATA_WIDTH : integer range 1 to 16 := 8;
Expand Down Expand Up @@ -34,11 +36,13 @@ architecture behavioral of zero_pad is

-- counter
signal int_ch_in : integer range 0 to C_CH - 1 := 0;
signal int_ch_out : integer range 0 to C_CH := 0;
signal int_row : integer range 0 to C_IMG_HEIGHT - 1 := 0;
signal int_col : integer range 0 to C_IMG_WIDTH - 1 := 0;
signal int_pixel_to_pad : integer range 0 to C_IMG_WIDTH_OUT + C_PAD_LEFT + 1 := 0;

signal sl_pixel_padded : std_logic := '0';
signal sl_padding_valid : std_logic := '0';

signal sl_output_valid : std_logic := '0';
signal slv_data_out : std_logic_vector(C_DATA_WIDTH - 1 downto 0);

Expand All @@ -48,46 +52,74 @@ architecture behavioral of zero_pad is

begin

proc_pad : process (isl_clk) is
i_pixel_counter_in : entity util.pixel_counter(single_process)
generic map (
C_HEIGHT => C_IMG_HEIGHT,
C_WIDTH => C_IMG_WIDTH,
C_CHANNEL => C_CH
)
port map (
isl_clk => isl_clk,
isl_reset => isl_start,
isl_valid => isl_valid,
oint_pixel => open,
oint_row => int_row,
oint_column => int_col,
oint_channel => int_ch_in
);

sl_padding_valid <= '1' when state = PAD_PIXEL and sl_pixel_padded = '0' else
'0';
i_channel_counter_out : entity util.basic_counter
generic map (
C_MAX => C_CH
)
port map (
isl_clk => isl_clk,
isl_reset => isl_start,
isl_valid => sl_padding_valid,
oint_count => open,
osl_maximum => sl_pixel_padded
);

-- Determine the image position to set int_pixel_to_pad.
-- There are three possibilities for padding:
-- 1. at the start of the image
-- 2. after each row
-- 3. at the end of the image

-- TODO: Fix padding at start/end for C_PAD > 1.
proc_pixel_to_pad : process (isl_clk) is
begin

if (rising_edge(isl_clk)) then
-- Determine the image position to set int_pixel_to_pad.
-- There are three possibilities for padding:
-- 1. at the start of the image
-- 2. after each row
-- 3. at the end of the image
if (isl_start = '1') then
-- padding at the start of the image
-- TODO: fix for C_PAD > 1
int_pixel_to_pad <= C_IMG_WIDTH_OUT + C_PAD_LEFT;
-- prevent problems with STRIDE /= KERNEL_SIZE at multiple images
int_row <= 0;
int_col <= 0;
state <= IDLE;
elsif (isl_valid = '1') then
if (int_ch_in < C_CH - 1) then
int_ch_in <= int_ch_in + 1;
else
int_ch_in <= 0;
if (int_col < C_IMG_WIDTH - 1) then
int_col <= int_col + 1;
else
int_col <= 0;
-- padding after each row
int_pixel_to_pad <= C_PAD_RIGHT + C_PAD_LEFT;
if (int_row < C_IMG_HEIGHT - 1) then
int_row <= int_row + 1;
else
int_row <= 0;
-- padding at the end of the image
-- TODO: fix for C_PAD > 1
int_pixel_to_pad <= C_PAD_BOTTOM * (C_IMG_WIDTH_OUT + C_PAD_RIGHT);
end if;
if (int_ch_in >= C_CH - 1 and int_col >= C_IMG_WIDTH - 1) then
-- padding after each row
int_pixel_to_pad <= C_PAD_RIGHT + C_PAD_LEFT;

if (int_row >= C_IMG_HEIGHT - 1) then
-- padding at the end of the image
int_pixel_to_pad <= C_PAD_BOTTOM * (C_IMG_WIDTH_OUT + C_PAD_RIGHT);
end if;
end if;
end if;

if (int_pixel_to_pad > 0 and isl_get = '1' and state = PAD) then
assert isl_valid = '0';
int_pixel_to_pad <= int_pixel_to_pad - 1;
end if;
end if;

end process proc_pixel_to_pad;

proc_fsm : process (isl_clk) is
begin

if (rising_edge(isl_clk)) then
-- states are dependent on current state and int_pixel_to_pad
case state is

Expand All @@ -99,20 +131,17 @@ begin
when PAD =>
if (int_pixel_to_pad > 0) then
if (isl_get = '1') then
state <= PAD_PIXEL;
int_pixel_to_pad <= int_pixel_to_pad - 1;
state <= PAD_PIXEL;
end if;
else
state <= FORWARD_DATA;
end if;

when PAD_PIXEL =>
if (int_ch_out < C_CH) then
int_ch_out <= int_ch_out + 1;
if (sl_pixel_padded = '0') then
sl_output_valid <= '1';
slv_data_out <= (others => '0');
else
int_ch_out <= 0;
sl_output_valid <= '0';
state <= PAD;
end if;
Expand All @@ -128,7 +157,7 @@ begin

end if;

end process proc_pad;
end process proc_fsm;

osl_valid <= sl_output_valid;
oslv_data <= slv_data_out;
Expand Down

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