add convenience function for slice assignment

marph91 · Mar 28, 2021 · c419ea8 · c419ea8
1 parent 0f83c80
commit c419ea8
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Showing 3 changed files with 19 additions and 9 deletions.
diff --git a/src/convolution.vhd b/src/convolution.vhd
@@ -71,7 +71,7 @@ begin
  v_usig_popcount := v_usig_popcount + 1;
  end if;
  end loop;
- slv_popcount((slice + 1) * C_INPUT_BITWIDTH_ADDER - 1 downto slice * C_INPUT_BITWIDTH_ADDER) <= std_logic_vector(v_usig_popcount);
+ assign_slice(slv_popcount, slice, std_logic_vector(v_usig_popcount));
  end loop;
 
  sl_add <= '1';
@@ -130,10 +130,10 @@ begin
  else
  v_slv_output_datum := std_logic_vector(-signed(v_slv_input_datum));
  end if;
- slv_product((v_int_index + 1) * C_PRODUCT_BITWIDTH - 1 downto v_int_index * C_PRODUCT_BITWIDTH) <= v_slv_output_datum;
+ assign_slice(slv_product, v_int_index, v_slv_output_datum);
  end loop;
  end loop;
- sl_add  <= '1';
+ sl_add <= '1';
  end if;
  end if;
 

diff --git a/src/util/array_pkg.vhd b/src/util/array_pkg.vhd
@@ -22,10 +22,12 @@ package array_pkg is
 
  function array_to_slv (array_in : t_kernel_array) return std_logic_vector;
 
- function get_slice (vector: std_logic_vector; int_byte_index : natural; int_slice_size : natural) return std_logic_vector;
+ function get_slice (vector: std_logic_vector; int_index : natural; int_slice_size : natural) return std_logic_vector;
 
  function get_fastest_increment (vector: std_logic_vector; int_index : natural; int_slice_size : natural) return std_logic_vector;
 
+ procedure assign_slice (signal vector : inout std_logic_vector; int_index : in natural; value : in std_logic_vector);
+
 end package array_pkg;
 
 package body array_pkg is
@@ -46,6 +48,7 @@ package body array_pkg is
  for current_row in array_in(0)'RANGE(2) loop
  for current_col in array_in(0)'RANGE(1) loop
  for current_channel in array_in'RANGE loop
+ -- TODO: How to support assign_slice for variable vector? Overloading is not possible.
  out_index_high := (current_channel + current_col * channel + current_row * cols * channel + 1) * bitwidth - 1;
  out_index_low := (current_channel + current_col * channel + current_row * cols * channel) * bitwidth;
  slv_out(out_index_high downto out_index_low) := array_in(current_channel)(current_col, current_row);
@@ -55,9 +58,9 @@ package body array_pkg is
  return slv_out;
  end function;
 
- function get_slice (vector: std_logic_vector; int_byte_index : natural; int_slice_size : natural) return std_logic_vector is
+ function get_slice (vector: std_logic_vector; int_index : natural; int_slice_size : natural) return std_logic_vector is
  begin
- return vector((int_byte_index + 1) * int_slice_size - 1 downto int_byte_index * int_slice_size);
+ return vector((int_index + 1) * int_slice_size - 1 downto int_index * int_slice_size);
  end function;
 
  function get_fastest_increment (vector: std_logic_vector; int_index : natural; int_slice_size : natural) return std_logic_vector is
@@ -69,4 +72,11 @@ package body array_pkg is
  return vector_out;
  end function;
 
+ procedure assign_slice (signal vector : inout std_logic_vector; int_index : in natural; value : in std_logic_vector) is
+ variable v_int_slice_size : integer;
+ begin
+ v_int_slice_size := value'length;
+ vector((int_index + 1) * v_int_slice_size - 1 downto int_index * v_int_slice_size) <= value;
+ end procedure;
+
 end package body array_pkg;
diff --git a/src/window_ctrl/line_buffer.vhd b/src/window_ctrl/line_buffer.vhd
@@ -91,9 +91,9 @@ begin
 
  if (rising_edge(isl_clk)) then
  if (isl_valid = '1') then
- a_data_out(0) <= islv_data;
- for i in 1 to C_KERNEL_SIZE - 1 loop
- a_data_out(i) <= slv_bram_data_out(i * C_BITWIDTH - 1 downto (i - 1) * C_BITWIDTH);
+ a_data_out(0)  <= islv_data;
+ for i in 0 to C_KERNEL_SIZE - 2 loop
+ a_data_out(i + 1) <= get_slice(slv_bram_data_out, i, C_BITWIDTH);
  end loop;
  end if;