resize with explicit number instead of other signal

This is done as a workaround for a ghdl synthesis bug.
marph91 · Mar 21, 2021 · ab11a7b · ab11a7b
1 parent e581163
commit ab11a7b
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/src/util/adder_tree.vhd b/src/util/adder_tree.vhd
@@ -55,9 +55,9 @@ architecture rtl of adder_tree is
 
  if (C_UNSIGNED = 1) then
  -- Pad a zero (sign) bit in case of unsigned input.
- v_sum_init(i) := resize(signed('0' & v_input_datum), v_sum_init(0));
+ v_sum_init(i) := resize(signed('0' & v_input_datum), v_sum_init(0)'length);
  else
- v_sum_init(i) := resize(signed(v_input_datum), v_sum_init(0));
+ v_sum_init(i) := resize(signed(v_input_datum), v_sum_init(0)'length);
  end if;
 
  end loop;