rework RAM and ROM

Makefile

@@ -20,6 +20,8 @@ SOURCES_UTIL = \
  $(ROOT_DIR)/src/util/array_pkg.vhd \
  $(ROOT_DIR)/src/util/math_pkg.vhd \
  $(ROOT_DIR)/src/util/bram.vhd \
+ $(ROOT_DIR)/src/util/bram_dual_port.vhd \
+ $(ROOT_DIR)/src/util/brom.vhd \
  $(ROOT_DIR)/src/util/basic_counter.vhd \
  $(ROOT_DIR)/src/util/pixel_counter.vhd \
  $(ROOT_DIR)/src/util/adder_tree.vhd \
@@ -53,14 +55,10 @@ bnn.json: toplevel
 
 bnn_out.config: bnn.json
  cd build/syn && \
- export PYTHONHOME=/home/martin/anaconda3 && \
- export LD_LIBRARY_PATH=$(LD_LIBRARY_PATH):/home/martin/anaconda3/lib && \
- nextpnr-ecp5 --85k --package CABGA381 --json bnn.json --lpf ../../syn/ulx3s_v20.lpf --textcfg bnn_out.config
+ nextpnr-ecp5 --85k --package CABGA381 --json bnn.json --lpf ../../syn/ulx3s_v20.lpf --textcfg bnn_out.config --lpf-allow-unconstrained
 
 bnn.bit: bnn_out.config
  cd build/syn && \
- export PYTHONHOME=/home/martin/anaconda3 && \
- export LD_LIBRARY_PATH=$(LD_LIBRARY_PATH):/home/martin/anaconda3/lib && \
  ecppack bnn_out.config bnn.bit
 
 prog:

src/util/bram.vhd

@@ -5,9 +5,8 @@ library ieee;
 
 entity bram is
  generic (
- C_DATA_WIDTH : integer;
- C_ADDR_WIDTH : integer;
- C_SIZE : integer
+ C_DATA_WIDTH : integer := 8;
+ C_ADDR_WIDTH : integer := 9
  );
  port (
  isl_clk : in std_logic;
@@ -21,11 +20,10 @@ end entity bram;
 
 architecture behavioral of bram is
 
- type t_ram is array(0 to C_SIZE - 1) of std_logic_vector(C_DATA_WIDTH - 1 downto 0);
+ type t_ram is array(0 to 2 ** C_ADDR_WIDTH - 1) of std_logic_vector(C_DATA_WIDTH - 1 downto 0);
+
+ signal a_ram : t_ram;
 
- signal a_ram : t_ram;
- attribute ram_style : string;
- attribute ram_style of a_ram : signal is "block";
  signal slv_data : std_logic_vector(C_DATA_WIDTH - 1 downto 0);
 
 begin

src/util/bram_dual_port.vhd

@@ -0,0 +1,50 @@
+
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+
+entity bram_dual_port is
+ generic (
+ C_DATA_WIDTH : integer := 8;
+ C_ADDR_WIDTH : integer := 9
+ );
+ port (
+ isl_wclk : in std_logic;
+ isl_rclk : in std_logic;
+ isl_we : in std_logic;
+ islv_waddr : in std_logic_vector(C_ADDR_WIDTH - 1 downto 0);
+ islv_data : in std_logic_vector(C_DATA_WIDTH - 1 downto 0);
+ islv_raddr : in std_logic_vector(C_ADDR_WIDTH - 1 downto 0);
+ oslv_data : out std_logic_vector(C_DATA_WIDTH - 1 downto 0)
+ );
+end entity bram_dual_port;
+
+architecture behavioral of bram_dual_port is
+
+ type t_ram is array(0 to 2 ** C_ADDR_WIDTH - 1) of std_logic_vector(C_DATA_WIDTH - 1 downto 0);
+
+ signal a_ram : t_ram;
+
+begin
+
+ proc_write : process (isl_wclk) is
+ begin
+
+ if (rising_edge(isl_wclk)) then
+ if (isl_we = '1') then
+ a_ram(to_integer(unsigned(islv_waddr))) <= islv_data;
+ end if;
+ end if;
+
+ end process proc_write;
+
+ proc_read : process (isl_rclk) is
+ begin
+
+ if (rising_edge(isl_rclk)) then
+ oslv_data <= a_ram(to_integer(unsigned(islv_raddr)));
+ end if;
+
+ end process proc_read;
+
+end architecture behavioral;

src/util/brom.vhd

@@ -0,0 +1,33 @@
+
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+
+entity brom is
+ generic (
+ C_DATA_WIDTH : integer := 8;
+ C_ADDR_WIDTH : integer := 9;
+ C_INIT_VALUE : std_logic_vector(C_ADDR_WIDTH * C_DATA_WIDTH - 1 downto 0) := (others => '1')
+ );
+ port (
+ islv_addr : in std_logic_vector(C_ADDR_WIDTH - 1 downto 0);
+ oslv_data : out std_logic_vector(C_DATA_WIDTH - 1 downto 0)
+ );
+end entity brom;
+
+architecture behavioral of brom is
+
+begin
+
+ proc_bram : process (islv_addr) is
+
+ variable int_addr : integer range 0 to 2 ** C_ADDR_WIDTH - 1;
+
+ begin
+
+ int_addr := to_integer(unsigned(islv_addr));
+ oslv_data <= C_INIT_VALUE((int_addr + 1) * C_DATA_WIDTH - 1 downto int_addr * C_DATA_WIDTH);
+
+ end process proc_bram;
+
+end architecture behavioral;

src/window_ctrl/line_buffer.vhd

@@ -47,8 +47,7 @@ begin
  i_bram : entity util.bram
  generic map (
  C_DATA_WIDTH => C_BRAM_DATA_WIDTH,
- C_ADDR_WIDTH => C_BRAM_ADDR_WIDTH,
- C_SIZE => C_BRAM_SIZE
+ C_ADDR_WIDTH => C_BRAM_ADDR_WIDTH
  )
  port map (
  isl_clk => isl_clk,