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prepare loading weights from files
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This is currently blocked by ghdl/ghdl#1661.
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marph91 committed Feb 23, 2021
1 parent ce6bcdb commit 5f9f9a2
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Showing 6 changed files with 65 additions and 18 deletions.
3 changes: 3 additions & 0 deletions .gitmodules
Original file line number Diff line number Diff line change
@@ -0,0 +1,3 @@
[submodule "submodules/JSON-for-VHDL"]
path = submodules/JSON-for-VHDL
url = https://github.com/Paebbels/JSON-for-VHDL.git
3 changes: 2 additions & 1 deletion sim/conftest.py
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
import os

from test_utils.extra_libs import analyze_util, analyze_window_ctrl_lib
from test_utils.extra_libs import analyze_json, analyze_util, analyze_window_ctrl_lib

# https://stackoverflow.com/questions/44624407/how-to-reduce-log-line-size-in-cocotb
os.environ["COCOTB_REDUCED_LOG_FMT"] = "1"
Expand All @@ -15,5 +15,6 @@ def pytest_addoption(parser):


def pytest_configure(config):
analyze_json()
analyze_util()
analyze_window_ctrl_lib()
22 changes: 16 additions & 6 deletions sim/test_utils/extra_libs.py
Original file line number Diff line number Diff line change
Expand Up @@ -9,13 +9,25 @@

STD = "--std=08"
WORK_DIR = "sim_build"
ABSOLUTE_PATH = pathlib.Path(__file__).parent.absolute()


def analyze_json():
work = "json"
source_path = ABSOLUTE_PATH / ".." / ".." / "submodules" / "JSON-for-VHDL" / "src"
source_files = get_files(source_path, "*.vhdl")

if outdated(f"{WORK_DIR}/{work}-obj08.cf", source_files):
os.makedirs(f"{WORK_DIR}", exist_ok=True)

analyze_command = ["ghdl", "-i", STD, f"--work={work}", f"--workdir={WORK_DIR}"]
analyze_command.extend(source_files)
subprocess.run(analyze_command, check=True)


def analyze_util():
work = "util"
source_path = (
pathlib.Path(__file__).parent.absolute() / ".." / ".." / "src" / "util"
)
source_path = ABSOLUTE_PATH / ".." / ".." / "src" / "util"
source_files = get_files(source_path, "*.vhd")

if outdated(f"{WORK_DIR}/{work}-obj08.cf", source_files):
Expand All @@ -30,9 +42,7 @@ def analyze_window_ctrl_lib():
analyze_util()

work = "window_ctrl_lib"
source_path = (
pathlib.Path(__file__).parent.absolute() / ".." / ".." / "src" / "window_ctrl"
)
source_path = ABSOLUTE_PATH / ".." / ".." / "src" / "window_ctrl"
source_files = get_files(source_path, "*.vhd")

if outdated(f"{WORK_DIR}/{work}-obj08.cf", source_files):
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51 changes: 40 additions & 11 deletions src/processing_element.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,9 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library json;
use json.json.all;

library cnn_lib;

library util;
Expand All @@ -22,17 +25,18 @@ entity processing_element is
C_OUTPUT_CHANNEL : integer := 8;

C_IMG_WIDTH : integer := 4;
C_IMG_HEIGHT : integer := 4
C_IMG_HEIGHT : integer := 4;

C_WEIGHTS_FILE : string := "../sim/weights.json";
C_LAYER_NAME : string := "pe1"
);
port (
isl_clk : in std_logic;
isl_start : in std_logic;
isl_valid : in std_logic;
islv_weights : in std_logic_vector(C_CONVOLUTION_KERNEL_SIZE ** 2 * C_INPUT_CHANNEL * C_OUTPUT_CHANNEL - 1 downto 0);
islv_threshold : in std_logic_vector(log2(C_CONVOLUTION_KERNEL_SIZE ** 2 * C_INPUT_CHANNEL + 1) * C_OUTPUT_CHANNEL - 1 downto 0);
islv_data : in std_logic_vector(7 downto 0);
oslv_data : out std_logic_vector(7 downto 0);
osl_valid : out std_logic
isl_clk : in std_logic;
isl_start : in std_logic;
isl_valid : in std_logic;
islv_data : in std_logic_vector(7 downto 0);
oslv_data : out std_logic_vector(7 downto 0);
osl_valid : out std_logic
);
end entity processing_element;

Expand All @@ -44,6 +48,31 @@ architecture behavioral of processing_element is
signal sl_valid_out : std_logic := '0';
signal slv_data_out : std_logic_vector(oslv_data'range);

-- constant C_JSON_CONTENT : t_json := jsonLoad(C_WEIGHTS_FILE);
-- constant C_WEIGHTS : integer_vector := jsonGetIntegerArray(C_JSON_CONTENT, "weights"); -- TODO: C_LAYER_NAME
-- constant C_THRESHOLDS : integer_vector := jsonGetIntegerArray(C_JSON_CONTENT, "thresholds");

-- TODO: verify correct order

function concatenate_integer_vector (input_vector : integer_vector; bitwidth : natural) return std_logic_vector is
variable concatenated_integers : std_logic_vector(input_vector'length * bitwidth - 1 downto 0);
begin
report to_string(input_vector(0)) severity note;
for index in input_vector'range loop
concatenated_integers((index + 1) * bitwidth - 1 downto index * bitwidth) := std_logic_vector(to_unsigned(input_vector(index), bitwidth));
end loop;
return concatenated_integers;
end function;

-- TODO: Obtain bitwidths from json.
constant C_TOTAL_INPUT_SIZE : integer := C_CONVOLUTION_KERNEL_SIZE ** 2 * C_INPUT_CHANNEL;
constant C_BITWIDTH_WEIGHTS : integer := 1;
constant C_BITWIDTH_THRESHOLDS : integer := log2(C_TOTAL_INPUT_SIZE + 1);
-- signal slv_weights : std_logic_vector(C_BITWIDTH_WEIGHTS * C_TOTAL_INPUT_SIZE * C_OUTPUT_CHANNEL - 1 downto 0) := concatenate_integer_vector(C_WEIGHTS, C_BITWIDTH_WEIGHTS);
-- signal slv_threshold : std_logic_vector(C_BITWIDTH_THRESHOLDS * C_OUTPUT_CHANNEL - 1 downto 0) := concatenate_integer_vector(C_THRESHOLDS, C_BITWIDTH_THRESHOLDS);
signal slv_weights : std_logic_vector(C_BITWIDTH_WEIGHTS * C_TOTAL_INPUT_SIZE * C_OUTPUT_CHANNEL - 1 downto 0) := (others => '1');
signal slv_threshold : std_logic_vector(C_BITWIDTH_THRESHOLDS * C_OUTPUT_CHANNEL - 1 downto 0) := (others => '0');

begin

i_window_convolution_activation : entity cnn_lib.window_convolution_activation
Expand All @@ -62,8 +91,8 @@ begin
isl_start => isl_start,
isl_valid => isl_valid,
islv_data => islv_data,
islv_weights => islv_weights,
islv_threshold => islv_threshold,
islv_weights => slv_weights,
islv_threshold => slv_threshold,
oslv_data => slv_data_convolution,
osl_valid => sl_valid_convolution
);
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1 change: 1 addition & 0 deletions submodules/JSON-for-VHDL
Submodule JSON-for-VHDL added at c8a6f5
3 changes: 3 additions & 0 deletions vhdl_ls.toml
Original file line number Diff line number Diff line change
@@ -1,4 +1,7 @@
[libraries]
json.files = [
"submodules/JSON-for-VHDL/src/*.vhdl"
]
util.files = [
"src/util/*.vhd",
]
Expand Down

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