CPU #12
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added 30 commits
September 5, 2016 21:20
Makefile has a couple decent goals:
test_alu: tests the ALU (verilog testbench for VHDL code!)
test_core: Tests the core, uses verilog top module to make sure it
stops
clean: cleans. Builds in build directory, maybe rethink it a bit
Currently pretty untested, but the core simulates & gives bus logs.
Deciding on memory interface between core and memory controller is next
step
Also, modified ClockAndResetGenerator to operate on seconds (so
everything agrees - verilog #1 is in seconds when blended with VHDL
apparently)
Updated Makefile to actually use the build directory & synopsys setup Added more synopsys generated files to .gitignore
Removed all extra signals from CPU (kept FIQ since it was integrated in, could remove later if needed). Added AN.DB to Makefile removes Start of system verilog core_tb in core_tb.sv
…repo. Still need to modify makefile
…ironment variables for ROM data file names, and core_tb reads from environment, so only one file needs to be changed to change ROM
Cleaned up monitor statement (no warning for out of bounds access) Cleaned up reset logic Remove clean from test_core makefile goal - caused simulator to fail rebuild & start Added reset to zero for memory
Address muxing done based on last address (since reads sequential)
memory module takes start & size and determines whether to output or not System works - Gets to instruction where CPSR: 0x1f->0x3f, then PC offset is wrong (but we're in thumb mode). Who knows....
ARM7TDMIS_TOP:
- Added Addr input for ControlLogic and DataAddrLow output (see
below)
- Changed ADDRLow input to IPDR to DataAddrLow
ControlLogic:
- Changed PcIncStep/AdrIncStep to change with THUMB mode switch
- Set ThumbDecoderEn to the CPSR flag
- Added logic to set AddrLow for IPDR based on address that
instruction was fetched at (DataAddrLow output)
IPDR:
- No notable changes
ThumbDecoder:
- Set BL(31:28) to be a valid condition
Current problem - THUMB decoder doesn't respect ARM THUMB BL semantics
…th memory interface
added 23 commits
November 5, 2016 14:14
benchmarks now. Added a sea of debug signals to core, to be removed. Changed cpu_top to actually use pause
Added FFF0-FFF9 region to memory controller. Added defines for FFF0-FFF9 region
…ory for sim memory
game_pak_init region. Added files from long emulation of bios to git.
…tes to mem interface
Conflicts: audio/audio_top.sv
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👍 |
mara-kr
pushed a commit
that referenced
this pull request
Dec 12, 2016
* Added VHDL ARM7TDMI Core from https://en.pudn.com/downloads168/sourcecode/embed/detail775435_en.html * Added core from "random guy on the internet" Makefile has a couple decent goals: test_alu: tests the ALU (verilog testbench for VHDL code!) test_core: Tests the core, uses verilog top module to make sure it stops clean: cleans. Builds in build directory, maybe rethink it a bit Currently pretty untested, but the core simulates & gives bus logs. Deciding on memory interface between core and memory controller is next step Also, modified ClockAndResetGenerator to operate on seconds (so everything agrees - verilog #1 is in seconds when blended with VHDL apparently) * Removed the storm core - can find it again if needed, but probably won't * Changed ARM7TDMI to cpu - more accurate folder name * Files got removed with branch name change, readded Updated Makefile to actually use the build directory & synopsys setup Added more synopsys generated files to .gitignore * Changed list of core_sim files to work with new Makefile * Removed LOCK and DMORE signals * Removed CFGBIGEND signal - it was unused * Moved files for VHLD test system to old_core_test Removed all extra signals from CPU (kept FIQ since it was integrated in, could remove later if needed). Added AN.DB to Makefile removes Start of system verilog core_tb in core_tb.sv * Finished core TB with a couple TODOs left. Added core_sim_defines to repo. Still need to modify makefile * Finished core_tb, modified makefile to use, core_tb compiles * Made BusLog output nicer - only prints once per read * Added logic for address mux in TB to ignore don't care addresses * Added pause, changed Makefile/core_tb to so that Makefile exports environment variables for ROM data file names, and core_tb reads from environment, so only one file needs to be changed to change ROM * Fixed bug in core_tb => WE was always high Cleaned up monitor statement (no warning for out of bounds access) Cleaned up reset logic Remove clean from test_core makefile goal - caused simulator to fail rebuild & start Added reset to zero for memory * Changed monitor to print out registers * Fixed memory address issues - address all 32bits, Address muxing done based on last address (since reads sequential) * Re-architected core_tb memory system - rdata is now a bus, each memory module takes start & size and determines whether to output or not System works - Gets to instruction where CPSR: 0x1f->0x3f, then PC offset is wrong (but we're in thumb mode). Who knows.... * Started full implementation of Thumb decoder * Completed ThumbDecoder & it compiles. * Lots of Fixes: ARM7TDMIS_TOP: - Added Addr input for ControlLogic and DataAddrLow output (see below) - Changed ADDRLow input to IPDR to DataAddrLow ControlLogic: - Changed PcIncStep/AdrIncStep to change with THUMB mode switch - Set ThumbDecoderEn to the CPSR flag - Added logic to set AddrLow for IPDR based on address that instruction was fetched at (DataAddrLow output) IPDR: - No notable changes ThumbDecoder: - Set BL(31:28) to be a valid condition Current problem - THUMB decoder doesn't respect ARM THUMB BL semantics * Updated gitignore with some new files * Added rom files to repo * Removed BUS_LOG_EN - it isn't worth capturing (needs to be updated with memory interface * Core makes it through pixels.elf, LR is off for one cycle? * Added testing infrastructure to test core with automation * Makefile changes, remove out.txt * QOL changes to testing infra - files to diff actually get put in build dir * Changed BusMon to only monitor writes. Writes are showing up in memory - should be good. * Removed ARM7TDMI/* from gitignore, added busLog file * Made diff formatting easier to read + columns * Added reset for memory back - BIOS code was getting don't cares for 0x04000300 * Removed unnecessary logic from Blink signal * Changed makefile & TB for fixing LR bug * Fixed bug where r1 was set to 0xfffffe00 & 0xfffffe04, then set to them again. Problem was with AdrIncStep and LastAddr value * Fixed bug where AdrIncStep was +2 when exiting THUMB mode (diff problem was with r0->0x300) * Changed setup to match BIOS * Set PC[0] to be zero always for address alignment * Fixed bug where LR address in thumb mode didn't have lowest bit set * Fixed error where LDM was getting rotated addresses * added memory definitions, added some unused infrastructure to testbench * Added extra files in CPU directory * Added wrapper SV wrapper for CPU synthesis * Added CPU to gba_top interface * Fixed (another) bug in the CPU with AdrIncStep - CPU works well on benchmarks now. Added a sea of debug signals to core, to be removed. Changed cpu_top to actually use pause * Fixed bug in addr inc step - was held for a cycle too long with STM in thumb mode * Final bugfixes in CPU - works for 135000 instructions to emulator * Added Makefile goal for ./simv, added memory region with 0xFFF0-0xFFF9 that BIOS expects * Added IF/ACK register to memory controller. Added FFF0-FFF9 region to memory controller. Added defines for FFF0-FFF9 region * Added Mode output for CPU, interrupts working, added mirroring of memory for sim memory * Interrupt controller implemented. Added hex files for LOZ and game_pak_init region. Added files from long emulation of bios to git. * Updated GBA top for new CPU interface + interrupt controller and updates to mem interface * Syntax fixes in gba_top, changed mem_top to have region mirroring * Added r4-r7 as debug signals, fixed syntax errors in int_controller and mem_top * Syntax fixes in timer/audio_top, integrated into gba_top * removed a bunch of files that weren't needed * removed .regs files for short runs * removed ALU test files * Removed multiplier and shifter files * Added DMA to gba_top, changed clocking wizard in audio_top * Added Audio I/O to constraints, added more modules to GBA top * Syntax fixes - switching work to integration branch
mara-kr
pushed a commit
that referenced
this pull request
Dec 12, 2016
* Added VHDL ARM7TDMI Core from https://en.pudn.com/downloads168/sourcecode/embed/detail775435_en.html * Added core from "random guy on the internet" Makefile has a couple decent goals: test_alu: tests the ALU (verilog testbench for VHDL code!) test_core: Tests the core, uses verilog top module to make sure it stops clean: cleans. Builds in build directory, maybe rethink it a bit Currently pretty untested, but the core simulates & gives bus logs. Deciding on memory interface between core and memory controller is next step Also, modified ClockAndResetGenerator to operate on seconds (so everything agrees - verilog #1 is in seconds when blended with VHDL apparently) * Removed the storm core - can find it again if needed, but probably won't * Changed ARM7TDMI to cpu - more accurate folder name * Files got removed with branch name change, readded Updated Makefile to actually use the build directory & synopsys setup Added more synopsys generated files to .gitignore * Changed list of core_sim files to work with new Makefile * Removed LOCK and DMORE signals * Removed CFGBIGEND signal - it was unused * Moved files for VHLD test system to old_core_test Removed all extra signals from CPU (kept FIQ since it was integrated in, could remove later if needed). Added AN.DB to Makefile removes Start of system verilog core_tb in core_tb.sv * Finished core TB with a couple TODOs left. Added core_sim_defines to repo. Still need to modify makefile * Finished core_tb, modified makefile to use, core_tb compiles * Made BusLog output nicer - only prints once per read * Added logic for address mux in TB to ignore don't care addresses * Added pause, changed Makefile/core_tb to so that Makefile exports environment variables for ROM data file names, and core_tb reads from environment, so only one file needs to be changed to change ROM * Fixed bug in core_tb => WE was always high Cleaned up monitor statement (no warning for out of bounds access) Cleaned up reset logic Remove clean from test_core makefile goal - caused simulator to fail rebuild & start Added reset to zero for memory * Changed monitor to print out registers * Fixed memory address issues - address all 32bits, Address muxing done based on last address (since reads sequential) * Re-architected core_tb memory system - rdata is now a bus, each memory module takes start & size and determines whether to output or not System works - Gets to instruction where CPSR: 0x1f->0x3f, then PC offset is wrong (but we're in thumb mode). Who knows.... * Started full implementation of Thumb decoder * Completed ThumbDecoder & it compiles. * Lots of Fixes: ARM7TDMIS_TOP: - Added Addr input for ControlLogic and DataAddrLow output (see below) - Changed ADDRLow input to IPDR to DataAddrLow ControlLogic: - Changed PcIncStep/AdrIncStep to change with THUMB mode switch - Set ThumbDecoderEn to the CPSR flag - Added logic to set AddrLow for IPDR based on address that instruction was fetched at (DataAddrLow output) IPDR: - No notable changes ThumbDecoder: - Set BL(31:28) to be a valid condition Current problem - THUMB decoder doesn't respect ARM THUMB BL semantics * Updated gitignore with some new files * Added rom files to repo * Removed BUS_LOG_EN - it isn't worth capturing (needs to be updated with memory interface * Core makes it through pixels.elf, LR is off for one cycle? * Added testing infrastructure to test core with automation * Makefile changes, remove out.txt * QOL changes to testing infra - files to diff actually get put in build dir * Changed BusMon to only monitor writes. Writes are showing up in memory - should be good. * Removed ARM7TDMI/* from gitignore, added busLog file * Made diff formatting easier to read + columns * Added reset for memory back - BIOS code was getting don't cares for 0x04000300 * Removed unnecessary logic from Blink signal * Changed makefile & TB for fixing LR bug * Fixed bug where r1 was set to 0xfffffe00 & 0xfffffe04, then set to them again. Problem was with AdrIncStep and LastAddr value * Fixed bug where AdrIncStep was +2 when exiting THUMB mode (diff problem was with r0->0x300) * Changed setup to match BIOS * Set PC[0] to be zero always for address alignment * Fixed bug where LR address in thumb mode didn't have lowest bit set * Fixed error where LDM was getting rotated addresses * added memory definitions, added some unused infrastructure to testbench * Added extra files in CPU directory * Added wrapper SV wrapper for CPU synthesis * Added CPU to gba_top interface * Fixed (another) bug in the CPU with AdrIncStep - CPU works well on benchmarks now. Added a sea of debug signals to core, to be removed. Changed cpu_top to actually use pause * Fixed bug in addr inc step - was held for a cycle too long with STM in thumb mode * Final bugfixes in CPU - works for 135000 instructions to emulator * Added Makefile goal for ./simv, added memory region with 0xFFF0-0xFFF9 that BIOS expects * Added IF/ACK register to memory controller. Added FFF0-FFF9 region to memory controller. Added defines for FFF0-FFF9 region * Added Mode output for CPU, interrupts working, added mirroring of memory for sim memory * Interrupt controller implemented. Added hex files for LOZ and game_pak_init region. Added files from long emulation of bios to git. * Updated GBA top for new CPU interface + interrupt controller and updates to mem interface * Syntax fixes in gba_top, changed mem_top to have region mirroring * Added r4-r7 as debug signals, fixed syntax errors in int_controller and mem_top * Syntax fixes in timer/audio_top, integrated into gba_top * removed a bunch of files that weren't needed * removed .regs files for short runs * removed ALU test files * Removed multiplier and shifter files * Added DMA to gba_top, changed clocking wizard in audio_top * Added Audio I/O to constraints, added more modules to GBA top * Syntax fixes - switching work to integration branch
mara-kr
pushed a commit
that referenced
this pull request
Dec 12, 2016
* Added VHDL ARM7TDMI Core from https://en.pudn.com/downloads168/sourcecode/embed/detail775435_en.html * Added core from "random guy on the internet" Makefile has a couple decent goals: test_alu: tests the ALU (verilog testbench for VHDL code!) test_core: Tests the core, uses verilog top module to make sure it stops clean: cleans. Builds in build directory, maybe rethink it a bit Currently pretty untested, but the core simulates & gives bus logs. Deciding on memory interface between core and memory controller is next step Also, modified ClockAndResetGenerator to operate on seconds (so everything agrees - verilog #1 is in seconds when blended with VHDL apparently) * Removed the storm core - can find it again if needed, but probably won't * Changed ARM7TDMI to cpu - more accurate folder name * Files got removed with branch name change, readded Updated Makefile to actually use the build directory & synopsys setup Added more synopsys generated files to .gitignore * Changed list of core_sim files to work with new Makefile * Removed LOCK and DMORE signals * Removed CFGBIGEND signal - it was unused * Moved files for VHLD test system to old_core_test Removed all extra signals from CPU (kept FIQ since it was integrated in, could remove later if needed). Added AN.DB to Makefile removes Start of system verilog core_tb in core_tb.sv * Finished core TB with a couple TODOs left. Added core_sim_defines to repo. Still need to modify makefile * Finished core_tb, modified makefile to use, core_tb compiles * Made BusLog output nicer - only prints once per read * Added logic for address mux in TB to ignore don't care addresses * Added pause, changed Makefile/core_tb to so that Makefile exports environment variables for ROM data file names, and core_tb reads from environment, so only one file needs to be changed to change ROM * Fixed bug in core_tb => WE was always high Cleaned up monitor statement (no warning for out of bounds access) Cleaned up reset logic Remove clean from test_core makefile goal - caused simulator to fail rebuild & start Added reset to zero for memory * Changed monitor to print out registers * Fixed memory address issues - address all 32bits, Address muxing done based on last address (since reads sequential) * Re-architected core_tb memory system - rdata is now a bus, each memory module takes start & size and determines whether to output or not System works - Gets to instruction where CPSR: 0x1f->0x3f, then PC offset is wrong (but we're in thumb mode). Who knows.... * Started full implementation of Thumb decoder * Completed ThumbDecoder & it compiles. * Lots of Fixes: ARM7TDMIS_TOP: - Added Addr input for ControlLogic and DataAddrLow output (see below) - Changed ADDRLow input to IPDR to DataAddrLow ControlLogic: - Changed PcIncStep/AdrIncStep to change with THUMB mode switch - Set ThumbDecoderEn to the CPSR flag - Added logic to set AddrLow for IPDR based on address that instruction was fetched at (DataAddrLow output) IPDR: - No notable changes ThumbDecoder: - Set BL(31:28) to be a valid condition Current problem - THUMB decoder doesn't respect ARM THUMB BL semantics * Updated gitignore with some new files * Added rom files to repo * Removed BUS_LOG_EN - it isn't worth capturing (needs to be updated with memory interface * Core makes it through pixels.elf, LR is off for one cycle? * Added testing infrastructure to test core with automation * Makefile changes, remove out.txt * QOL changes to testing infra - files to diff actually get put in build dir * Changed BusMon to only monitor writes. Writes are showing up in memory - should be good. * Removed ARM7TDMI/* from gitignore, added busLog file * Made diff formatting easier to read + columns * Added reset for memory back - BIOS code was getting don't cares for 0x04000300 * Removed unnecessary logic from Blink signal * Changed makefile & TB for fixing LR bug * Fixed bug where r1 was set to 0xfffffe00 & 0xfffffe04, then set to them again. Problem was with AdrIncStep and LastAddr value * Fixed bug where AdrIncStep was +2 when exiting THUMB mode (diff problem was with r0->0x300) * Changed setup to match BIOS * Set PC[0] to be zero always for address alignment * Fixed bug where LR address in thumb mode didn't have lowest bit set * Fixed error where LDM was getting rotated addresses * added memory definitions, added some unused infrastructure to testbench * Added extra files in CPU directory * Added wrapper SV wrapper for CPU synthesis * Added CPU to gba_top interface * Fixed (another) bug in the CPU with AdrIncStep - CPU works well on benchmarks now. Added a sea of debug signals to core, to be removed. Changed cpu_top to actually use pause * Fixed bug in addr inc step - was held for a cycle too long with STM in thumb mode * Final bugfixes in CPU - works for 135000 instructions to emulator * Added Makefile goal for ./simv, added memory region with 0xFFF0-0xFFF9 that BIOS expects * Added IF/ACK register to memory controller. Added FFF0-FFF9 region to memory controller. Added defines for FFF0-FFF9 region * Added Mode output for CPU, interrupts working, added mirroring of memory for sim memory * Interrupt controller implemented. Added hex files for LOZ and game_pak_init region. Added files from long emulation of bios to git. * Updated GBA top for new CPU interface + interrupt controller and updates to mem interface * Syntax fixes in gba_top, changed mem_top to have region mirroring * Added r4-r7 as debug signals, fixed syntax errors in int_controller and mem_top * Syntax fixes in timer/audio_top, integrated into gba_top * removed a bunch of files that weren't needed * removed .regs files for short runs * removed ALU test files * Removed multiplier and shifter files * Added DMA to gba_top, changed clocking wizard in audio_top * Added Audio I/O to constraints, added more modules to GBA top * Syntax fixes - switching work to integration branch
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