Skip to content
View manu38gre's full-sized avatar

Block or report manu38gre

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results

🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.

VHDL 22 8 Updated Dec 21, 2021

Création d un système d arrosage automatique, piloté via Home Assistant

1 Updated Aug 18, 2023

DSP IIR realtime filter library written in C++

C++ 632 138 Updated Aug 12, 2024

A Collection of Useful C++ Classes for Digital Signal Processing

C++ 1,836 377 Updated Aug 5, 2023

Generate SVG schematics and block diagrams without a mouse.

Python 25 3 Updated Mar 29, 2024

Index of the fully open source process design kits (PDKs) maintained by Google.

85 8 Updated Sep 4, 2022

A series of posts about QEMU internals:

1,348 143 Updated Nov 3, 2023

RISC-V Open Source Supervisor Binary Interface

C 1,008 503 Updated Sep 27, 2024

Constrained random stimuli generation for C++ and SystemC

C++ 48 13 Updated Nov 29, 2023

Python package for writing Value Change Dump (VCD) files.

Python 107 40 Updated Sep 3, 2024

Standard Cell Library based Memory Compiler using FF/Latch cells

Verilog 1 Updated Sep 6, 2022

A python implementation of the FSDB flat-file streaming database.

Python 7 2 Updated Aug 30, 2024

Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.

Python 54 8 Updated Aug 18, 2021

Constrained RAndom Verification Enviroment (CRAVE)

C++ 15 7 Updated Nov 23, 2023

ZPU Evo(lution), an enhanced ZPU microprocessor design in VHDL to embed within an FPGA including SoC functionality. Project currently uses Altera Cyclone devices.

VHDL 15 3 Updated Sep 4, 2022

ZPUino HDL implementation

VHDL 88 54 Updated Aug 6, 2018
C 50 31 Updated Apr 25, 2017

A highly-configurable and compact variant of the ZPU processor core

VHDL 34 11 Updated Sep 12, 2015

ZPU - the worlds smallest 32 bit CPU with GCC toolchain

VHDL 16 4 Updated Jul 17, 2014

The Zylin ZPU

VHDL 238 32 Updated Apr 21, 2015

Public repository for PySysC, (From SC Common Practices Subgroup)

Python 48 6 Updated Dec 26, 2023

A header only C++11 library for functional coverage

C++ 1 Updated Jul 13, 2022

A SystemC wrapper for the Unicorn Engine (https://www.unicorn-engine.org/)

C++ 2 2 Updated Aug 6, 2022

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

C 7,547 1,337 Updated Oct 13, 2024

Public repository for the SC Common Practices Subgroup

Python 8 1 Updated May 16, 2024

The UVM written in Python

Python 367 70 Updated Jul 20, 2024

OpenModelica is an open-source Modelica-based modeling and simulation environment intended for industrial and academic usage.

Modelica 823 304 Updated Oct 14, 2024

An (old) Emacs mode for Taskjuggler files

Emacs Lisp 5 5 Updated Jun 17, 2021

Fabric generator and CAD tools

Python 147 33 Updated Oct 9, 2024
Next