Stars
🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.
Création d un système d arrosage automatique, piloté via Home Assistant
A Collection of Useful C++ Classes for Digital Signal Processing
Generate SVG schematics and block diagrams without a mouse.
Index of the fully open source process design kits (PDKs) maintained by Google.
RISC-V Open Source Supervisor Binary Interface
Constrained random stimuli generation for C++ and SystemC
Python package for writing Value Change Dump (VCD) files.
openpowerwtf / DFFRAM
Forked from AUCOHL/DFFRAMStandard Cell Library based Memory Compiler using FF/Latch cells
A python implementation of the FSDB flat-file streaming database.
Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
Constrained RAndom Verification Enviroment (CRAVE)
ZPU Evo(lution), an enhanced ZPU microprocessor design in VHDL to embed within an FPGA including SoC functionality. Project currently uses Altera Cyclone devices.
A highly-configurable and compact variant of the ZPU processor core
ZPU - the worlds smallest 32 bit CPU with GCC toolchain
Public repository for PySysC, (From SC Common Practices Subgroup)
Minres / fc4sc
Forked from amiq-consulting/fc4scA header only C++11 library for functional coverage
A SystemC wrapper for the Unicorn Engine (https://www.unicorn-engine.org/)
Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)
Minres / PySysC
Forked from accellera-official/PySysCPublic repository for the SC Common Practices Subgroup
OpenModelica is an open-source Modelica-based modeling and simulation environment intended for industrial and academic usage.
An (old) Emacs mode for Taskjuggler files
Fabric generator and CAD tools