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Vale basic support for PowerPC architecture
This patch adds Vale support for PowerPC architecture, The patch implements 64-bit little-endian specification of PPC arch in addition to use Power ISA v.3.0 for the instruction set hence the supported processors are POWER9+. The patch also tries to have a relative interface with x64simple implementation by using the same naming convention and common functions to make the code more maintainable. The following features are implemented: - General-purpose registers. - Vector registers (with the compatibility to use in VSR-specific instructions). - Condition Register (CR) and Fixed-Point Exception Register (XER) to update the comparison status and to handle carry and overflow occurrences. - Validation, evaluation and update functions for registers. - Procedure conditional statements (If, Else, While) that support register-register and register-immediate comparisons. Unlike x64, using those statements update the flags accordingly at run-time rather than havoc them to get refreshed values of Condition Register (CR). - Basic and vector instruction support for which have use-cases. - Print functions for the supported instructions with bare register names, GCC has -mregnames option to assemble named registers for PowerPC but it's GCC-specific option and disabled by default. - GCC assembly printer support. - Lemmas functions for high-level functions in addition to ensure the results of basic and vector instructions. - Negative constant support in assembly in addition to ensure the bounds of instruction operands and memory offsets. - Memory interface to deal with memory addresses and operands. - Implement Copy16 function in PPC64LE.Test.Memcpy module.
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