Release v4.6.0

macronix · Aug 30, 2023 · e28c088 · e28c088
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diff --git a/README.md b/README.md
@@ -10,7 +10,7 @@ FSP uses an open software ecosystem and provides flexibility in using your prefe
 
 ### Current Release
 
-[FSP v4.5.0](https://github.com/renesas/fsp/releases/tag/v4.5.0)
+[FSP v4.6.0](https://github.com/renesas/fsp/releases/tag/v4.6.0)
 
 ### Supported RA MCU Kits
 
@@ -73,14 +73,15 @@ For a list of software modules packaged with FSP, see [Supported Software](SUPPO
 - FSP versions of 4.1.0 and later require a minimum e² studio version of 2022-10.
 - FSP versions of 4.3.0 and later require a minimum e² studio version of 2023-01.
 - FSP versions of 4.4.0 and later require a minimum e² studio version of 2023-04.
+- FSP versions of 4.6.0 and later require a minimum e² studio version of 2023-07.
 
 If you have already installed a previous FSP release that included e² studio then you can download the packs separately. These are available for download under the Assets section for each release. There is a zipped version, FSP_Packs_\<version\>.zip, that will work on any supported OS. There is also a self-extracting installer version, FSP_Packs_\<version\>.exe, that will work on Windows.
 
 When using the zipped version of the packs the zip file should be extracted into the e² studio support area. This directory is typically found under the user's home directory with a path such as `~/.eclipse/com.renesas.platform_2047834950`. The number on the end of the path is unique to each e² studio installation. If you have two e² studio installations then you will have two directories with names of the format `~/.eclipse/com.renesas.platform_<unique_number>`. Please note that e² studio must have been run at least once for this directory to be created. You can find the support area for a particular e² studio installation by clicking `Help >> About e² studio`. In the window that pops up click `Installation Details` and choose the `Support Folders` tab. The e² studio support area path will be shown.
 
 #### For new users that are using FSP with e² studio
 
-1. Download the FSP with e² studio Installer from the Assets section of the [current release](https://github.com/renesas/fsp/releases/tag/v4.5.0).
+1. Download the FSP with e² studio Installer from the Assets section of the [current release](https://github.com/renesas/fsp/releases/tag/v4.6.0).
 2. Run the installer. This will install the e² studio tool, FSP packs, GCC toolchain and other tools required to use this software. No additional installations are required.
 
 #### If using RA Smart Configurator (RASC) with IAR Embedded Workbench or Keil MDK ####

diff --git a/SUPPORTED_SOFTWARE.md b/SUPPORTED_SOFTWARE.md
@@ -110,6 +110,7 @@
  * [Motor inertia estimation (rm_motor_inertia_estimate)](https://renesas.github.io/fsp/group___m_o_t_o_r___i_n_e_r_t_i_a___e_s_t_i_m_a_t_e.html)
  * [Motor return origin function (rm_motor_return_origin)](https://renesas.github.io/fsp/group___m_o_t_o_r___r_e_t_u_r_n___o_r_i_g_i_n.html)
  * [Motor vector control with induction sensor (rm_motor_induction)](https://renesas.github.io/fsp/group___m_o_t_o_r___i_n_d_u_c_t_i_o_n.html)
+ * [Shared ADC module (on rm_motor_driver)](https://renesas.github.io/fsp/group___m_o_t_o_r___d_r_i_v_e_r.html)
  * Networking
  * Bluetooth Low Energy Mesh Network modules
  * [BLE Mesh (rm_ble_mesh)](https://renesas.github.io/fsp/group___r_m___b_l_e___m_e_s_h.html)
@@ -359,7 +360,7 @@
  * [RYZ012 SPP Driver Layer](https://renesas.github.io/fsp/group___b_l_e___a_b_s___s_p_p.html)
  * [TinyCBOR](https://github.com/intel/tinycbor/)
  * [WiFi Common](https://docs.aws.amazon.com/freertos/latest/userguide/freertos-wifi.html)
- * [WiFi Onchip DA16xxx Driver using r_sci_uart (rm_wifi_onchip_da16xxx)](https://renesas.github.io/fsp/group___w_i_f_i___o_n_c_h_i_p___d_a16200.html)
+ * [WiFi Onchip DA16xxx Driver using r_sci_uart (rm_wifi_onchip_da16xxx)](https://renesas.github.io/fsp/group___w_i_f_i___o_n_c_h_i_p___d_a16_x_x_x.html)
  * [WiFi Onchip Silex Driver using r_sci_uart (rm_wifi_onchip_silex)](https://renesas.github.io/fsp/group___w_i_f_i___o_n_c_h_i_p___s_i_l_e_x.html)
  * Security
  * [Azure RTOS NetX Crypto HW Acceleration (rm_netx_secure_crypto)](https://renesas.github.io/fsp/group___r_m___n_e_t_x___s_e_c_u_r_e___c_r_y_p_t_o.html)

diff --git a/ra/fsp/inc/api/fsp_common_api.h b/ra/fsp/inc/api/fsp_common_api.h
@@ -300,15 +300,14 @@ typedef enum e_fsp_err
  FSP_ERR_WIFI_UNKNOWN_AT_CMD = 70007, ///< DA16200 Unknown AT command Error
  FSP_ERR_WIFI_INSUF_PARAM = 70008, ///< DA16200 Insufficient parameter
  FSP_ERR_WIFI_TOO_MANY_PARAMS = 70009, ///< DA16200 Too many parameters
- FSP_ERR_WIFI_INV_PARAM_VAL = 70010, ///< DA16200 Wrong parameter value 
+ FSP_ERR_WIFI_INV_PARAM_VAL = 70010, ///< DA16200 Wrong parameter value
  FSP_ERR_WIFI_NO_RESULT = 70011, ///< DA16200 No result
  FSP_ERR_WIFI_RSP_BUF_OVFLW = 70012, ///< DA16200 Response buffer overflow
- FSP_ERR_WIFI_FUNC_NOT_CONFIG = 70013, ///< DA16200 Function is not configured 
+ FSP_ERR_WIFI_FUNC_NOT_CONFIG = 70013, ///< DA16200 Function is not configured
  FSP_ERR_WIFI_NVRAM_WR_FAIL = 70014, ///< DA16200 NVRAM write failure
  FSP_ERR_WIFI_RET_MEM_WR_FAIL = 70015, ///< DA16200 Retention memory write failure
  FSP_ERR_WIFI_UNKNOWN_ERR = 70016, ///< DA16200 unknown error
 
-
  /* Start of SF_CELLULAR Specific */
  FSP_ERR_CELLULAR_CONFIG_FAILED = 80000, ///< Cellular module Configuration failed.
  FSP_ERR_CELLULAR_INIT_FAILED = 80001, ///< Cellular module initialization failed.

diff --git a/ra/fsp/inc/api/r_adc_api.h b/ra/fsp/inc/api/r_adc_api.h
@@ -183,9 +183,9 @@ typedef enum e_adc_group_mask
 /** ADC states. */
 typedef enum e_adc_state
 {
- ADC_STATE_IDLE = 0,   ///< ADC is idle
- ADC_STATE_SCAN_IN_PROGRESS = 1,   ///< ADC scan in progress
- ADC_STATE_CALIBRATION_IN_PROGRESS = 2,  ///< ADC calibration in progress - Not used by all ADC instances
+ ADC_STATE_IDLE   = 0, ///< ADC is idle
+ ADC_STATE_SCAN_IN_PROGRESS   = 1, ///< ADC scan in progress
+ ADC_STATE_CALIBRATION_IN_PROGRESS = 2, ///< ADC calibration in progress - Not used by all ADC instances
 } adc_state_t;
 
 /** ADC status. */

diff --git a/ra/fsp/inc/api/r_crc_api.h b/ra/fsp/inc/api/r_crc_api.h
@@ -148,11 +148,12 @@ typedef void crc_ctrl_t;
 /** User configuration structure, used in open function */
 typedef struct st_crc_cfg
 {
- crc_polynomial_t polynomial; ///< CRC Generating Polynomial Switching (GPS)
- crc_bit_order_t bit_order; ///< CRC Calculation Switching (LMS)
+ crc_polynomial_t polynomial; ///< CRC Generating Polynomial Switching (GPS)
+ crc_bit_order_t bit_order; ///< CRC Calculation Switching (LMS)
+
  /* crc_snoop_address_t is to be deprecated. */
- int32_t snoop_address; ///< Register Snoop Address (CRCSA)
- void const   * p_extend; ///< CRC Hardware Dependent Configuration
+ int32_t snoop_address; ///< Register Snoop Address (CRCSA)
+ void const * p_extend;   ///< CRC Hardware Dependent Configuration
 } crc_cfg_t;
 
 /** CRC driver structure. General CRC functions implemented at the HAL layer will follow this API. */

diff --git a/ra/fsp/inc/api/r_ioport_api.h b/ra/fsp/inc/api/r_ioport_api.h
@@ -16,7 +16,8 @@
  * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
  * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
  * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
- **********************************************************************************************************************/ 
+ **********************************************************************************************************************/
+
 /*******************************************************************************************************************//**
  * @ingroup RENESAS_INTERFACES
  * @defgroup IOPORT_API I/O Port Interface
@@ -69,11 +70,11 @@ typedef enum e_ioport_peripheral
 
  /** Pin will function as an AGT peripheral pin */
  IOPORT_PERIPHERAL_AGT = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET),
- 
-  /** Pin will function as an AGT peripheral pin */
+
+  /** Pin will function as an AGT peripheral pin */
  IOPORT_PERIPHERAL_AGTW = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET),
- 
-  /** Pin will function as an AGT peripheral pin */
+
+  /** Pin will function as an AGT peripheral pin */
  IOPORT_PERIPHERAL_AGT1 = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET),
 
  /** Pin will function as a GPT peripheral pin */
@@ -116,12 +117,14 @@ typedef enum e_ioport_peripheral
  IOPORT_PERIPHERAL_LCDC = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
 
 #if BSP_FEATURE_SCI_UART_DE_IS_INVERTED
+
  /** Pin will function as an SCI peripheral DEn pin */
  IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
 
  /** Pin will function as an SCI DEn peripheral pin */
  IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
 #else
+
  /** Pin will function as an SCI peripheral DEn pin */
  IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
 
@@ -132,10 +135,9 @@ typedef enum e_ioport_peripheral
  /** Pin will function as a DALI peripheral pin */
  IOPORT_PERIPHERAL_DALI = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
 
-
  /** Pin will function as a CEU peripheral pin */
  IOPORT_PERIPHERAL_CEU = (0x0FUL << IOPORT_PRV_PFS_PSEL_OFFSET),
- 
+
  /** Pin will function as a CAN peripheral pin */
  IOPORT_PERIPHERAL_CAN = (0x10UL << IOPORT_PRV_PFS_PSEL_OFFSET),
 
@@ -193,11 +195,11 @@ typedef enum e_ioport_peripheral
  /** Pin will function as a PGAOUT peripheral pin */
  IOPORT_PERIPHERAL_PGAOUT1 = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
 
- /** Pin will function as a MIPI peripheral pin */
- IOPORT_PERIPHERAL_MIPI = (0x1FUL << IOPORT_PRV_PFS_PSEL_OFFSET),
-
  /** Pin will function as a ULPT peripheral pin */
  IOPORT_PERIPHERAL_ULPT = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
+
+ /** Pin will function as a MIPI DSI peripheral pin */
+ IOPORT_PERIPHERAL_MIPI = (0x1FUL << IOPORT_PRV_PFS_PSEL_OFFSET),
 } ioport_peripheral_t;
 
 /** Options to configure pin functions */