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Test designs for Sayma boards (ddr3, drtio, amc-rtm link, jesd204b)

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doc
doc
 
 
firmware
firmware
 
 
gateware
gateware
 
 
sim
sim
 
 
test
test
 
 
README
README
 
 
TODO
TODO
 
 
clkgen.py
clkgen.py
 
 
litex_setup.py
litex_setup.py
 
 
load.py
load.py
 
 
sayma_amc.py
sayma_amc.py
 
 
sayma_rtm.py
sayma_rtm.py
 
 

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Test designs for Sayma boards (ddr3, drtio, serwb, jesd204b)

[> Status
---------
- ddr3: 32 bit and 64 bit ddr3 validated at 1Gbps/pin.
- drtio: MultiGTH validated with 2 lanes at 1.25Gbps.
- serwb: validated between AMC (Master) & RTM (Slave) @ 1.25Gbps.
- jesd204b: untested

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Test designs for Sayma boards (ddr3, drtio, amc-rtm link, jesd204b)

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