LPC: new SM #1
Closed
LPC: new SM #1
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
- merged both state machines into one - get rid of the counter, added many more states - obey the data size of memory accesses - handle the tar-sync-tar sequence at the end of write accesses This code needs many more tests!
added *.vpp to .gitignore
lpc_tb: added result check
call "make test" in order to run all testbenches
also suppressed output of the for loop in Makefile, target test
derive the module to test from the name of the testbench file (all until the first -)
added new mem read test with long and short sync
|
Hi @jal2 |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Hi,
you may have a look at my changes here - if you still care for this project.
I've added some tests (and Makefile will automatically detect and execute them). State machine in lpc.v supports memory cycles as well. There is something wrong in top.v, as I've added more wires in lpc.v interface (but the tools don't complain?).
Next I'll do some documentation based on top.v to better understand the wiring of the modules. I'm a newbie in Verilog and don't understand how the different clock domains (lpc and serial) are synced. A ringbuffer with async read/write which I found in the web looks ways more complex.
Cheers,
Joerg