implement ftdi fast opto serial mode

the ftdi fast opto serial mode is much faster than uart. it supports up to 50mhz clock.
lynxis · Nov 5, 2017 · be6dc41 · be6dc41
1 parent 6ab5602
commit be6dc41
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Showing 3 changed files with 20 additions and 12 deletions.
diff --git a/Makefile b/Makefile
@@ -1,6 +1,6 @@
 
 NAME=top
-DEPS=buffer.v bufferdomain.v lpc.v mem2serial.v ringbuffer.v uart_tx.v power_on_reset.v trigger_led.v pll.v
+DEPS=buffer.v bufferdomain.v lpc.v mem2serial.v ringbuffer.v uart_tx.v power_on_reset.v trigger_led.v pll.v ftdi.v
 
 $(NAME).bin: $(NAME).pcf $(NAME).v $(DEPS)
  yosys -p "synth_ice40 -blif $(NAME).blif" $(NAME).v $(DEPS)

diff --git a/top.pcf b/top.pcf
@@ -6,7 +6,10 @@ set_io lpc_ad[3] 116
 set_io lpc_frame 117
 set_io lpc_reset 118
 set_io ext_clock 21
-set_io uart_tx_pin 8
+set_io fsdi 9
+set_io fsclk 8
+set_io fscts 4
+set_io fsdo 7
 set_io lpc_clock_led 99
 set_io lpc_frame_led 98
 set_io lpc_reset_led 97

diff --git a/top.v b/top.v
@@ -5,7 +5,10 @@ module top #(parameter CLOCK_FREQ = 33_000_000, parameter BAUD_RATE = 921600)
  input lpc_frame,
  input lpc_reset,
  input ext_clock,
- output uart_tx_pin,
+ input fscts,
+ input fsdo,
+ output fsdi,
+ output fsclk,
  output lpc_clock_led,
  output lpc_frame_led,
  output lpc_reset_led,
@@ -107,15 +110,17 @@ module top #(parameter CLOCK_FREQ = 33_000_000, parameter BAUD_RATE = 921600)
  .uart_ready(uart_ready),
  .uart_data(uart_data));
 
- uart_tx #(.CLOCK_FREQ(CLOCK_FREQ), .BAUD_RATE(BAUD_RATE))
- SERIAL (
- .read_data(uart_data),
- .read_clock_enable(uart_clock_enable),
- .reset(reset),
- .ready(uart_ready),
- .tx(uart_tx_pin),
- .clock(main_clock),
- .uart_clock(uart_clock));
+ wire [1:0] state;
+ ftdi SERIAL (
+ .read_data(uart_data),
+ .read_clock_enable(uart_clock_enable),
+ .reset(reset),
+ .ready(uart_ready),
+ .fsdi(fsdi),
+ .fscts(fscts),
+ .state(state),
+ .clock(main_clock));
+ assign fsclk = main_clock;
 
  trigger_led TRIGGERLPC(
  .reset(reset),