Functional verification project for the CORE-V family of RISC-V cores.

First, have a look at the OpenHW Group's website to learn a bit more about who we are and what we are doing.
For first time users of CORE-V-VERIF, the Quick Start Guide in the CORE-V-VERIF Verification Strategy is the best place to start.

Various utilities for running tests and performing various verification-related activities in the core-v-verif repository.

Empty sub-directory into which the RTL from one or more of the CORE-V-CORES repositories is cloned.

Core-specific verification code.

Sources for the Verification Strategy document, DV plans, coding style guidelines and available coverage reports.

Common simulation Makefiles that support testbenches for all CORE-V cores.

Common components for the all CORE-V verification environments.

Verification components supported by third-parties.

We highly appreciate community contributions. You can get a sense of our current needs by reviewing the GitHub projects associated with this repository. Individual work-items within a project are defined as issues with a task label.

To ease our work of reviewing your contributions, please:

• Review CONTRIBUTING and our SV/UVM coding style guidelines.
• Split large contributions into smaller commits addressing individual changes or bug fixes. Do not mix unrelated changes into the same commit!
• Write meaningful commit messages.
• If asked to modify your changes, do fixup your commits and rebase your branch to maintain a clean history.

Some contributions to core-v-verif are supported by the TRISTAN and ISOLDE projects, which have received funding from the Key Digital Technologies Joint Undertaking (KDT JU), Austria, Belgium, Czechia, Finland, France, Germany, Italy, the Netherlands, Poland, Romania, Sweden, Switzerland, Spain and Turkey under grant agreements 101095947 and 101112274. The JU receives support from the European Union’s Horizon Europe research and innovation program.