Commits

Commits on Mar 11, 2018

armv7a: cache ttbcr and ttb0/1 on debug state entry
thinkfat
committedMar 11, 2018

Commits on Apr 23, 2017

board: introduce base config for TI BeagleBone family boards

thinkfat
authored and
FreddieChopin
committedApr 23, 2017

Commits on Feb 13, 2016

jtag ftdi: sample TDO on falling edge of TCK

thinkfat
authored and
nattgris
committedFeb 13, 2016

Commits on Jan 22, 2016

am437x: always use highest possible JTAG clock.

thinkfat
authored and
paulfertser
committedJan 22, 2016
adiv5: introduce optional dap_sync() function

thinkfat
authored and
paulfertser
committedJan 22, 2016
adi_v5_jtag: implement DAP WAIT support

thinkfat
authored and
paulfertser
committedJan 22, 2016

Commits on Dec 29, 2015

cortex_a: add 'dacrfixup' to cortex-a command group

thinkfat
authored and
nattgris
committedDec 29, 2015
AM335x: allow simultaneous debugging of A8 and M3 cores

thinkfat
authored and
nattgris
committedDec 29, 2015
arm_debug: optimize DP and AP reads over JTAG

thinkfat
authored and
nattgris
committedDec 29, 2015
cortex_a: select APB-AP as the default AP

thinkfat
authored and
nattgris
committedDec 29, 2015

Commits on Dec 1, 2015

cortex_a: fix fast-mode memory reads

thinkfat
authored and
paulfertser
committedDec 1, 2015

Commits on Nov 30, 2015

cortex_a: replace cortex_a_check_address function

thinkfat
authored and
paulfertser
committedNov 30, 2015
cortex_a: rework mmu manipulation

thinkfat
authored and
paulfertser
committedNov 30, 2015
cortex_a: force cache and tlb bypass when cpu is in debug state

thinkfat
authored and
paulfertser
committedNov 30, 2015
armv7a: fix-up dcache clean and flush functions inner loop pattern

thinkfat
authored and
paulfertser
committedNov 30, 2015
cortex_a: Update instruction cache after setting a soft breakpoint

thinkfat
authored and
paulfertser
committedNov 30, 2015
armv7a: correctly handle invalidation of inner data caches

thinkfat
authored and
paulfertser
committedNov 30, 2015
armv7a: fix debug messages regarding cache on/off state

thinkfat
authored and
paulfertser
committedNov 30, 2015
armv7a: rework automatic flush-on-write handling

thinkfat
authored and
paulfertser
committedNov 30, 2015
armv7a: add d-cache virtual address range flush function

thinkfat
authored and
paulfertser
committedNov 30, 2015
armv7a: remove indirection for cache info handler

thinkfat
authored and
paulfertser
committedNov 30, 2015
armv7a: fix handling of inner caches

thinkfat
authored and
paulfertser
committedNov 30, 2015
armv7a: remove special l2x flush-all and cache-info handlers

thinkfat
authored and
paulfertser
committedNov 30, 2015
armv7a: rename l2_cache to outer_cache

thinkfat
authored and
paulfertser
committedNov 30, 2015

Commits on Nov 5, 2015

armv7a: correct calculation of ttbr0_mask

thinkfat
authored and
FreddieChopin
committedNov 5, 2015
armv7a: re-read ttb information if ttbcr changes

thinkfat
authored and
FreddieChopin
committedNov 5, 2015

Commits on Nov 4, 2015

Revert "board: don't hardcode interface for ti_beaglebone"

thinkfat
authored and
FreddieChopin
committedNov 4, 2015

Commits on Nov 3, 2015

board: don't hardcode interface for ti_beaglebone

thinkfat
authored and
FreddieChopin
committedNov 3, 2015