cortex_m: fix stepping on FPB rev 1

Stepping in the maskisr auto mode sets breakpoint to step over interrupt service tasks. If the device has FPB rev 1, setting hard breakpoint is impossible on address over 0x1fffffff. Use soft type breakpoint for adresses over 0x1fffffff if FPB is rev 1. This may eventually fail if the code memory is not writeable, but there is nothing to do in such case. Change-Id: Ibdeeb506903a35d550b64f82c24c37a668de62b3 Signed-off-by: Tomas Vanek <[email protected]> Reviewed-on: https://openocd.zylin.com/4857 Tested-by: jenkins Reviewed-by: Antonio Borneo <[email protected]>
lobaro · Feb 4, 2019 · 4b998cb · 4b998cb
1 parent 5105e60
commit 4b998cb
Showing 1 changed file with 10 additions and 3 deletions.
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
@@ -877,10 +877,17 @@ static int cortex_m_step(struct target *target, int current,
  else {
 
  /* Set a temporary break point */
- if (breakpoint)
+ if (breakpoint) {
  retval = cortex_m_set_breakpoint(target, breakpoint);
- else
- retval = breakpoint_add(target, pc_value, 2, BKPT_HARD);
+ } else {
+ enum breakpoint_type type = BKPT_HARD;
+ if (cortex_m->fp_rev == 0 && pc_value > 0x1FFFFFFF) {
+ /* FPB rev.1 cannot handle such addr, try BKPT instr */
+ type = BKPT_SOFT;
+ }
+ retval = breakpoint_add(target, pc_value, 2, type);
+ }
+
  bool tmp_bp_set = (retval == ERROR_OK);
 
  /* No more breakpoints left, just do a step */