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Problem: On acquiring triggered acquisitions, the trigger detection has a jitter of about 4 (for the ADC/ADCSWAP rate) or 2 (for the other rates) for the acquired waveform. This is due to the trigger alignment logic at the acq_trigger module.
Possible Solution: Record the number of "off" trigger samples and subtract this number from the DDR trigger address at the ddr3_axis_wirte module
The text was updated successfully, but these errors were encountered:
Problem: On acquiring triggered acquisitions, the trigger detection has a jitter of about 4 (for the ADC/ADCSWAP rate) or 2 (for the other rates) for the acquired waveform. This is due to the trigger alignment logic at the
acq_trigger
module.Possible Solution: Record the number of "off" trigger samples and subtract this number from the DDR trigger address at the
ddr3_axis_wirte
moduleThe text was updated successfully, but these errors were encountered: