configs

18f/main.c

@@ -3,10 +3,123 @@
 #include <pic16/pic18f26k20.h>
 
 //#pragma from sddc manual? 
-// DS41303G-page 300 
-#pragma config FOSC = INTIO7, BOREN = OFF, WDTEN = OFF, MCLRE = OFF, STVREN = ON
-#pragma config LVP = OFF, CP0 = OFF, FCMEN = OFF, IESO = OFF
-
+// configs from http:https://electronics.stackexchange.com/questions/77308/problem-with-transmitting-data-from-pic18f45k20-c18-to-mcp23017
+// looks like start up with internal oscilator 16Mhz 1 MHz (Default after Reset)?
+
+// CONFIG1H
+
+#pragma config FOSC = INTIO67 // Oscillator Selection bits (Internal oscillator block, port function on RA6 and RA7)
+
+#pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
+
+#pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
+
+
+
+// CONFIG2L
+
+#pragma config PWRT = OFF // Power-up Timer Enable bit (PWRT disabled)
+
+#pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
+
+#pragma config BORV = 30 // Brown Out Reset Voltage bits (VBOR set to 3.0 V nominal)
+
+
+
+// CONFIG2H
+
+#pragma config WDTEN = OFF // Watchdog Timer Enable bit (WDT is controlled by SWDTEN bit of the WDTCON register)
+
+#pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768)
+
+
+
+// CONFIG3H
+
+#pragma config CCP2MX = PORTC // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
+
+#pragma config PBADEN = ON // PORTB A/D Enable bit (PORTB<4:0> pins are configured as analog input channels on Reset)
+
+#pragma config LPT1OSC = OFF // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation)
+
+#pragma config HFOFST = ON // HFINTOSC Fast Start-up (HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize.)
+
+#pragma config MCLRE = OFF // MCLR Pin Enable bit (RE3 input pin enabled; MCLR disabled)
+
+
+
+// CONFIG4L
+
+#pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
+
+#pragma config LVP = OFF // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
+
+#pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
+
+
+
+// CONFIG5L
+
+#pragma config CP0 = OFF // Code Protection Block 0 (Block 0 (000800-001FFFh) not code-protected)
+
+#pragma config CP1 = OFF // Code Protection Block 1 (Block 1 (002000-003FFFh) not code-protected)
+
+#pragma config CP2 = OFF // Code Protection Block 2 (Block 2 (004000-005FFFh) not code-protected)
+
+#pragma config CP3 = OFF // Code Protection Block 3 (Block 3 (006000-007FFFh) not code-protected)
+
+
+
+// CONFIG5H
+
+#pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
+
+#pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected)
+
+
+
+// CONFIG6L
+
+#pragma config WRT0 = OFF // Write Protection Block 0 (Block 0 (000800-001FFFh) not write-protected)
+
+#pragma config WRT1 = OFF // Write Protection Block 1 (Block 1 (002000-003FFFh) not write-protected)
+
+#pragma config WRT2 = OFF // Write Protection Block 2 (Block 2 (004000-005FFFh) not write-protected)
+
+#pragma config WRT3 = OFF // Write Protection Block 3 (Block 3 (006000-007FFFh) not write-protected)
+
+
+
+// CONFIG6H
+
+#pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
+
+#pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
+
+#pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected)
+
+
+
+// CONFIG7L
+
+#pragma config EBTR0 = OFF // Table Read Protection Block 0 (Block 0(000800-001FFFh) not protected from table reads executed in other blocks)
+
+#pragma config EBTR1 = OFF // Table Read Protection Block 1 (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks)
+
+#pragma config EBTR2 = OFF // Table Read Protection Block 2 (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks)
+
+#pragma config EBTR3 = OFF // Table Read Protection Block 3 (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks)
+
+
+
+// CONFIG7H
+
+#pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)
+
+
+
+
+
 
 void delay (void)
 {