pyverbs: Fix runtime warnings in Fedora 39

Adapt to Cython 3 to get rid of such warnings: "<frozen importlib._bootstrap>:241: UserWarning: enum class rdma_port_space not importable from pyverbs.librdmacm_enums. You are probably using a cpdef enum declared in a .pxd file that does not have a .py or .pyx file. <frozen importlib._bootstrap>:241: UserWarning: enum class ibv_send_flags not importable from pyverbs.libibverbs. You are probably using a cpdef enum declared in a .pxd file that does not have a .py or .pyx file." By adding empty .pyx files with the same name as current .pxd, or by renaming relevant .pxd files where it's possible. Signed-off-by: Edward Srouji <[email protected]>
linux-rdma · Jan 21, 2024 · c0377a2 · c0377a2
1 parent 0fa21ec
commit c0377a2
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Showing 20 changed files with 52 additions and 57 deletions.
diff --git a/pyverbs/CMakeLists.txt b/pyverbs/CMakeLists.txt
@@ -31,6 +31,10 @@ rdma_cython_module(pyverbs ""
  enums.pyx
  flow.pyx
  fork.pyx
+ libibverbs.pyx
+ libibverbs_enums.pyx
+ librdmacm.pyx
+ librdmacm_enums.pyx
  mem_alloc.pyx
  mr.pyx
  pd.pyx

diff --git a/pyverbs/libibverbs.pxd b/pyverbs/libibverbs.pxd
@@ -1,6 +1,8 @@
 # SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB)
 # Copyright (c) 2018, Mellanox Technologies. All rights reserved. See COPYING file
 
+#cython: language_level=3
+
 include 'libibverbs_enums.pxd'
 from libc.stdint cimport uint8_t, uint16_t, uint32_t, uint64_t
 from posix.time cimport timespec

diff --git a/pyverbs/libibverbs.pyx b/pyverbs/libibverbs.pyx
diff --git a/pyverbs/libibverbs_enums.pyx b/pyverbs/libibverbs_enums.pyx
diff --git a/pyverbs/librdmacm.pxd b/pyverbs/librdmacm.pxd
@@ -1,6 +1,8 @@
 # SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB)
 # Copyright (c) 2019, Mellanox Technologies. All rights reserved. See COPYING file
 
+#cython: language_level=3
+
 include 'libibverbs.pxd'
 include 'librdmacm_enums.pxd'
 from libc.stdint cimport uint8_t, uint32_t

diff --git a/pyverbs/librdmacm.pyx b/pyverbs/librdmacm.pyx
diff --git a/pyverbs/librdmacm_enums.pyx b/pyverbs/librdmacm_enums.pyx
diff --git a/pyverbs/providers/efa/CMakeLists.txt b/pyverbs/providers/efa/CMakeLists.txt
@@ -4,4 +4,5 @@
 rdma_cython_module(pyverbs/providers/efa efa
  efa_enums.pyx
  efadv.pyx
+ libefa.pyx
 )
diff --git a/pyverbs/providers/efa/efadv_enums.pxd → pyverbs/providers/efa/efa_enums.pxd b/pyverbs/providers/efa/efadv_enums.pxd → pyverbs/providers/efa/efa_enums.pxd
diff --git a/pyverbs/providers/efa/efa_enums.pyx b/pyverbs/providers/efa/efa_enums.pyx
@@ -1,22 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB)
-# Copyright 2020-2024 Amazon.com, Inc. or its affiliates. All rights reserved.
-
-#cython: language_level=3
-
-cdef extern from 'infiniband/efadv.h':
-
- cpdef enum:
- EFADV_DEVICE_ATTR_CAPS_RDMA_READ
- EFADV_DEVICE_ATTR_CAPS_CQ_WITH_SGID
- EFADV_DEVICE_ATTR_CAPS_RDMA_WRITE
-
- cpdef enum:
- EFADV_QP_DRIVER_TYPE_SRD
-
- cpdef enum:
- EFADV_WC_EX_WITH_SGID
-
- cpdef enum:
- EFADV_MR_ATTR_VALIDITY_RECV_IC_ID
- EFADV_MR_ATTR_VALIDITY_RDMA_READ_IC_ID
- EFADV_MR_ATTR_VALIDITY_RDMA_RECV_IC_ID

diff --git a/pyverbs/providers/efa/efadv.pyx b/pyverbs/providers/efa/efadv.pyx
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB)
 # Copyright 2020-2024 Amazon.com, Inc. or its affiliates. All rights reserved.
 
-cimport pyverbs.providers.efa.efadv_enums as dve
+cimport pyverbs.providers.efa.efa_enums as dve
 cimport pyverbs.providers.efa.libefa as dv
 
 from pyverbs.addr cimport GID

diff --git a/pyverbs/providers/efa/libefa.pxd b/pyverbs/providers/efa/libefa.pxd
@@ -1,6 +1,8 @@
 # SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB)
 # Copyright 2020-2024 Amazon.com, Inc. or its affiliates. All rights reserved.
 
+#cython: language_level=3
+
 from libc.stdint cimport uint8_t, uint16_t, uint32_t, uint64_t
 cimport pyverbs.libibverbs as v
 

diff --git a/pyverbs/providers/efa/libefa.pyx b/pyverbs/providers/efa/libefa.pyx
diff --git a/pyverbs/providers/mlx5/CMakeLists.txt b/pyverbs/providers/mlx5/CMakeLists.txt
@@ -7,6 +7,7 @@ rdma_cython_module(pyverbs/providers/mlx5 mlx5
  dr_matcher.pyx
  dr_rule.pyx
  dr_table.pyx
+ libmlx5.pyx
  mlx5_enums.pyx
  mlx5_vfio.pyx
  mlx5dv.pyx

diff --git a/pyverbs/providers/mlx5/libmlx5.pxd b/pyverbs/providers/mlx5/libmlx5.pxd
@@ -1,7 +1,9 @@
 # SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB)
 # Copyright (c) 2019 Mellanox Technologies, Inc. All rights reserved. See COPYING file
 
-include 'mlx5dv_enums.pxd'
+#cython: language_level=3
+
+include 'mlx5_enums.pxd'
 
 from libc.stdint cimport uint8_t, uint16_t, uint32_t, uint64_t, uintptr_t
 from posix.types cimport off_t

diff --git a/pyverbs/providers/mlx5/libmlx5.pyx b/pyverbs/providers/mlx5/libmlx5.pyx
diff --git a/pyverbs/providers/mlx5/mlx5dv_enums.pxd → pyverbs/providers/mlx5/mlx5_enums.pxd b/pyverbs/providers/mlx5/mlx5dv_enums.pxd → pyverbs/providers/mlx5/mlx5_enums.pxd
@@ -305,21 +305,6 @@ cdef extern from 'infiniband/mlx5dv.h':
  cdef unsigned long long MLX5DV_QUERY_PORT_ESW_OWNER_VHCA_ID
 
 
-_MLX5DV_RES_TYPE_QP = MLX5DV_RES_TYPE_QP
-_MLX5DV_RES_TYPE_RWQ = MLX5DV_RES_TYPE_RWQ
-_MLX5DV_RES_TYPE_DBR = MLX5DV_RES_TYPE_DBR
-_MLX5DV_RES_TYPE_SRQ = MLX5DV_RES_TYPE_SRQ
-_MLX5DV_PP_ALLOC_FLAGS_DEDICATED_INDEX = MLX5DV_PP_ALLOC_FLAGS_DEDICATED_INDEX
-_MLX5DV_UAR_ALLOC_TYPE_BF = MLX5DV_UAR_ALLOC_TYPE_BF
-_MLX5DV_UAR_ALLOC_TYPE_NC = MLX5DV_UAR_ALLOC_TYPE_NC
-MLX5DV_QUERY_PORT_VPORT_ = MLX5DV_QUERY_PORT_VPORT
-MLX5DV_QUERY_PORT_VPORT_VHCA_ID_ = MLX5DV_QUERY_PORT_VPORT_VHCA_ID
-MLX5DV_QUERY_PORT_VPORT_STEERING_ICM_RX_ = MLX5DV_QUERY_PORT_VPORT_STEERING_ICM_RX
-MLX5DV_QUERY_PORT_VPORT_STEERING_ICM_TX_ = MLX5DV_QUERY_PORT_VPORT_STEERING_ICM_TX
-MLX5DV_QUERY_PORT_VPORT_REG_C0_ = MLX5DV_QUERY_PORT_VPORT_REG_C0
-MLX5DV_QUERY_PORT_ESW_OWNER_VHCA_ID_ = MLX5DV_QUERY_PORT_ESW_OWNER_VHCA_ID
-
-
 cdef extern from 'infiniband/mlx5_user_ioctl_verbs.h':
  cdef enum mlx5_ib_uapi_flow_table_type:
  pass
@@ -335,18 +320,3 @@ cdef extern from 'infiniband/mlx5_api.h':
  cdef int MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL
  cdef int MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2
  cdef int MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL
-
-MLX5DV_FLOW_TABLE_TYPE_RDMA_RX_ = MLX5DV_FLOW_TABLE_TYPE_RDMA_RX
-MLX5DV_FLOW_TABLE_TYPE_RDMA_TX_ = MLX5DV_FLOW_TABLE_TYPE_RDMA_TX
-MLX5DV_FLOW_TABLE_TYPE_NIC_RX_ = MLX5DV_FLOW_TABLE_TYPE_NIC_RX
-MLX5DV_FLOW_TABLE_TYPE_NIC_TX_ = MLX5DV_FLOW_TABLE_TYPE_NIC_TX
-MLX5DV_FLOW_TABLE_TYPE_FDB_ = MLX5DV_FLOW_TABLE_TYPE_FDB
-
-MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2_ = \
- MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2
-MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL_ = \
- MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL
-MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2_ = \
- MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2
-MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL_ = \
- MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL
diff --git a/pyverbs/providers/mlx5/mlx5_enums.pyx b/pyverbs/providers/mlx5/mlx5_enums.pyx
diff --git a/pyverbs/providers/mlx5/mlx5_enums.pyx b/pyverbs/providers/mlx5/mlx5_enums.pyx
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB)
+# Copyright (c) 2024 Nvidia All rights reserved.
+
+#cython: language_level=3
+
+_MLX5DV_RES_TYPE_QP = MLX5DV_RES_TYPE_QP
+_MLX5DV_RES_TYPE_RWQ = MLX5DV_RES_TYPE_RWQ
+_MLX5DV_RES_TYPE_DBR = MLX5DV_RES_TYPE_DBR
+_MLX5DV_RES_TYPE_SRQ = MLX5DV_RES_TYPE_SRQ
+_MLX5DV_PP_ALLOC_FLAGS_DEDICATED_INDEX = MLX5DV_PP_ALLOC_FLAGS_DEDICATED_INDEX
+_MLX5DV_UAR_ALLOC_TYPE_BF = MLX5DV_UAR_ALLOC_TYPE_BF
+_MLX5DV_UAR_ALLOC_TYPE_NC = MLX5DV_UAR_ALLOC_TYPE_NC
+
+MLX5DV_QUERY_PORT_VPORT_ = MLX5DV_QUERY_PORT_VPORT
+MLX5DV_QUERY_PORT_VPORT_VHCA_ID_ = MLX5DV_QUERY_PORT_VPORT_VHCA_ID
+MLX5DV_QUERY_PORT_VPORT_STEERING_ICM_RX_ = MLX5DV_QUERY_PORT_VPORT_STEERING_ICM_RX
+MLX5DV_QUERY_PORT_VPORT_STEERING_ICM_TX_ = MLX5DV_QUERY_PORT_VPORT_STEERING_ICM_TX
+MLX5DV_QUERY_PORT_VPORT_REG_C0_ = MLX5DV_QUERY_PORT_VPORT_REG_C0
+MLX5DV_QUERY_PORT_ESW_OWNER_VHCA_ID_ = MLX5DV_QUERY_PORT_ESW_OWNER_VHCA_ID
+
+MLX5DV_FLOW_TABLE_TYPE_RDMA_RX_ = MLX5DV_FLOW_TABLE_TYPE_RDMA_RX
+MLX5DV_FLOW_TABLE_TYPE_RDMA_TX_ = MLX5DV_FLOW_TABLE_TYPE_RDMA_TX
+MLX5DV_FLOW_TABLE_TYPE_NIC_RX_ = MLX5DV_FLOW_TABLE_TYPE_NIC_RX
+MLX5DV_FLOW_TABLE_TYPE_NIC_TX_ = MLX5DV_FLOW_TABLE_TYPE_NIC_TX
+MLX5DV_FLOW_TABLE_TYPE_FDB_ = MLX5DV_FLOW_TABLE_TYPE_FDB
+
+MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2_ = \
+ MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2
+MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL_ = \
+ MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL
+MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2_ = \
+ MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2
+MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL_ = \
+ MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL
diff --git a/pyverbs/providers/mlx5/mlx5dv.pyx b/pyverbs/providers/mlx5/mlx5dv.pyx
@@ -14,7 +14,7 @@ from pyverbs.providers.mlx5.mlx5dv_crypto cimport Mlx5CryptoLoginAttr, Mlx5Crypt
 from pyverbs.pyverbs_error import PyverbsUserError, PyverbsRDMAError, PyverbsError
 from pyverbs.providers.mlx5.dr_action cimport DrActionFlowCounter, DrActionDestTir
 from pyverbs.providers.mlx5.mlx5dv_sched cimport Mlx5dvSchedLeaf
-cimport pyverbs.providers.mlx5.mlx5dv_enums as dve
+cimport pyverbs.providers.mlx5.mlx5_enums as dve
 cimport pyverbs.providers.mlx5.libmlx5 as dv
 from pyverbs.mem_alloc import posix_memalign
 from pyverbs.qp cimport QPInitAttrEx, QPEx

diff --git a/pyverbs/providers/mlx5/mlx5dv_objects.pyx b/pyverbs/providers/mlx5/mlx5dv_objects.pyx
@@ -12,7 +12,7 @@ Note: This is not be confused with Mlx5<Obj> which holds the ibv_<obj>_ex that
 from libc.stdint cimport uintptr_t, uint32_t
 
 from pyverbs.pyverbs_error import PyverbsUserError, PyverbsRDMAError
-cimport pyverbs.providers.mlx5.mlx5dv_enums as dve
+cimport pyverbs.providers.mlx5.mlx5_enums as dve
 cimport pyverbs.libibverbs as v