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1. avmm-lvds-bridge avmm-lvds-bridge Public

   Cores for transfer Avalon-MM transaction through LVDS SERDES interface

   SystemVerilog 2

2. avalon-1wire-master avalon-1wire-master Public

   1-wire bus master core with Altera Avalon-MM slave interface

   SystemVerilog 1

3. emif16-avmm-bridge emif16-avmm-bridge Public

   Module for connect TI DSP to Altera Qsys Interconnect through EMIF16 interface

   SystemVerilog 1 1

4. altera-makefiles altera-makefiles Public

   Makefiles & scripts for Altera FPGA projects

   Makefile 2

5. avalon-1wire-master-example avalon-1wire-master-example Public

   Example of using Avalon 1-wire master core with DS18B20 sensors

   Tcl

6. picorv32 picorv32 Public

   Forked from YosysHQ/picorv32

   PicoRV32 - A Size-Optimized RISC-V CPU

   Verilog