The ZipCPU blog

Modular hardware build system

Yosys Open SYnthesis Suite

Logic synthesis and ABC based optimization

Mobile ALOHA: Learning Bimanual Mobile Manipulation with Low-Cost Whole-Body Teleoperation

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

A look ahead, round-robing parametrized arbiter written in Verilog.

An overview of TL-Verilog resources and projects

Veriloggen: A Mixed-Paradigm Hardware Construction Framework

NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network

Copy of webbhm/OpenAg-MVP-II

arduino scripts for MySensors IoT

📚 List of awesome university courses for learning Computer Science!

India's first Personal Food Computer

Bitcoin Core integration/staging tree

K-9 Mail – Open Source Email App for Android