A tool for converting pure-past LTL formulae to temporal testers, along with auxiliary tools.

Generate monitor circuits for LTL properties

past-ltl -> aiger circuit library.

A minimalistic and high-performance SAT solver

Using GNN and DQN to find a baetter branching heuristic for a CDCL Solver

A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.

Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization

Concolic Testing on RTL for Detecting Security Vulnerabilities

HAL – The Hardware Analyzer

work in progress, playing around with btor2 in rust

Generate testbench for your verilog module.

Fast Symbolic Repair of Hardware Design Code

Companion artifact for ASPLOS '24: Lifting Micro-Update Models from RTL

KtikZ provides a nice user interface for making pictures using TikZ.

PyTorch model to RTL flow for low latency inference

A modern hardware definition language and toolchain based on Python

Convert PDF to markdown quickly with high accuracy

py-aiger: A python library for manipulating sequential and combinatorial circuits encoded using `and` & `inverter` gates (AIGs).

AIGER And-Inverter-Graph Library

Code for transforming aiger expression into an equi-satisifabile aiger expression in CNF form.

List of awesome open source hardware tools, generators, and reusable designs

Automated Repair of Verilog Hardware Descriptions

The source code to the Voss II Hardware Verification Suite

C++ logic network library

ABC: System for Sequential Logic Synthesis and Formal Verification

📚 Solutions for C++ Primer 5th exercises.

code for privacy-preserving sat solver