Mail : [email protected]
- Computer Architecture
- RISC V
- SoC Design
- Digital circuit Design, RTL Design
- System Verilog, Verilog
- Synthesis, Equivalence Checking
- Basics of UPF and SDC
- Low Power Design
- Static Timing Analysis
- RTL-to-GDS flow
- Perl / Python / Tcl Scripting
- Bash/Csh Linux Shell
- Finite State Machine Design
- Computer Architecture
- Computer Hardware
- Simulation
- vcs
- xcelium
- Synthesis
- fusion compiler
- genus
- Static Checks ( Lint | CDC )
- spyglass
- jaspergold
- Equivalence Checking
- conformal
- Physical Design
- innovus
- virtuoso
- Timing
- tempus
- General
- git
- vim