A Chisel RTL generator for network-on-chip interconnects

Nyxstone: assembly / disassembly library based on LLVM, implemented in C++ with Rust and Python bindings, maintained by emproof.com

Wrappers around Rust's integer to check for constant-time-compatible usage

Code generation tool for control and status registers

3-stage RV32IMACZb* processor with debug

yosys, nextpnr, apicula and openFPGALoader in vscode using OSS-CAD-Suite

TexEtch is a Visual Studio Code extension designed to convert diagrams drawn in draw.io into text format. This text format can be easily integrated into your code base to provide better explanation…

vscode-openai seamlessly incorporates OpenAI features into VSCode, providing integration with SCM, Code Editor and Chat.

A High-performance Timing Analysis Tool for VLSI Systems

The testing ground for the future of portable SIMD in Rust

A minimal GPU design in Verilog to learn how GPUs work from the ground up

SLotH -- An SLH-DSA/SPHINCS+ Hash-Based Signature Accelerator

an experiment to run plugin in firtool pipeline

Easy SMT solver interaction

Search everything, instantly.

slang-based frontend for Yosys

Usable, easy and safe pure-Rust crypto

Comprehensive timing leak protection for Rust programs https://www.chosenplaintext.ca/open-source/rust-timing-shield/

Testing the Rust crypto library orion with dudect-bencher

An implementation of the DudeCT constant-time function tester

A Rust verification tool

A rust library for the Zarr storage format for multidimensional arrays and metadata

SCARR is a Side-Channel Analysis (SCA) framework

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…

Python/C/RTL cosimulation with Xilinx's xsim simulator

Create Draw.io (diagrams.net) drawings, with Python