Partition and Configuration Manager for SpiNNaker

This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning and computer architecture.

Software framework for Designing and Mapping a CNN onto neuromorphic chip with crossbar array of synapses.

Dataflow compiler for QNN inference on FPGAs

This repository contains generic VHDL implementation of modified booths algorithm (Radix 4) for both signed and unsigned (2's complement form) binary numbers.

VHDL implementation for a Matrix Multiplier

The CNN architecture elements implemented with RTL approach in VHDL.

BNN-to-FPGA framework, written in VHDL and Python