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pcapFromVerilog
pcapFromVerilog PublicSmall module that lets you read packets from a PCAP file to an AXI like interface. For use in testbenches
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wireshark-hwgen
wireshark-hwgen PublicFork of wireshark-tools (editcap), version 1.99.2 with additional support for new formats in utilities such as hwgen, a personal definition
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cache_performance
cache_performance PublicThis is a small example where the impact of the cache can be measure in a Linux environment
C 1
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circular_buffer
circular_buffer PublicA circular buffer implemented as an interface in system verilog
SystemVerilog 1
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msix-7series
msix-7series PublicImplementation of the MSI-X structure (table and PBA) in a BRAM memory. This module also offers the necessary interconnection for interact with the Xilinx 7 Series Integrated block for PCIe.
Verilog 2
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