Skip to content
View jasommer's full-sized avatar

Block or report jasommer

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results
Jupyter Notebook 10,422 1,290 Updated May 21, 2024

Tensorflow implementation of a Neural Turing Machine

Python 604 91 Updated Jul 15, 2021

High-speed simulator of convolutional spiking neural networks with at most one spike per neuron.

Jupyter Notebook 381 100 Updated Sep 7, 2021
Jupyter Notebook 42 11 Updated Sep 4, 2019

Toolbox for converting analog to spiking neural networks (ANN to SNN), and running them in a spiking neuron simulator.

Python 363 105 Updated Jan 13, 2023

What about coding a Spiking Neural Network using an automatic differentiation framework? In SNNs, there is a time axis and the neural network sees data throughout time, and activation functions are…

Jupyter Notebook 265 50 Updated Nov 6, 2022

Scan documents to PDF and more, as simply as possible.

C# 2,832 327 Updated Oct 5, 2024

An automated systematic design flow that couples model-based desing and simulation with high-level-synthesis

MATLAB 5 1 Updated Feb 11, 2020

PicoRV32 - A Size-Optimized RISC-V CPU

Verilog 3,138 755 Updated Jun 27, 2024

😎 A curated list of awesome RISC-V implementations

129 13 Updated Mar 12, 2023

Conway's Game of Life in FPGA

Verilog 30 Updated Apr 30, 2020

Bus bridges and other odds and ends

Verilog 486 101 Updated Jan 12, 2024

A simple RISC-V processor for use in FPGA designs.

VHDL 263 41 Updated Aug 19, 2024