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SystemVerilog_examples Public
This repository contains systemverilog codes for the purpose of learning modeling and design verification.
SystemVerilog UpdatedJul 19, 2024 -
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ibex Public
Forked from lowRISC/ibexIbex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
C++ Apache License 2.0 UpdatedJun 27, 2024 -
nnom Public
Forked from majianjia/nnomA higher-level Neural Network library for microcontrollers.
C Apache License 2.0 UpdatedJun 27, 2024