External Release v2024.04.01

This release updates XED according to Intel's latest APX spec (Rev-04), April 2024.
It includes:
  - Remove promoted SHA and KeyLocker EVEX instructions
  - Encoding update for URDMSR/UWRMSR
  - Addition of missing CPUID sensitivity for promoted POPCNT EVEX instruction
  - Update the handling of EVEX.U and reinterpretation to X4

General:
  - Enable a secured build using a new `--security-level` mfile.py knob (1->Medium, 2->High, 3->Highest).
    The default level is 1 (will be raised to 2 in a future release)
    Please expect performance degradation with level 3.
  - Drop the ICC/ICL build options using mfile.py

Add:
  - AMX: Support the restriction of illegal register combination (Solves #303)
  - Disassembler: Print sequential registers using "+(N-1)" notation
  - Add ENC2 support for Intel APX architecture (TBD: REX2 for EGPR support)
  - Add ENC2 support for KOP instructions

Fix:
  - ISA definition fixes (APX/MOVDIR64B missing operands, Fix CPUID for SYS{ENTER,EXIT}, fix MMX extensions)
  - RFLAGS: Fix width definition and wrong duplicated operands for several instructions (Solves #320)
  - Fix CPL definition for ENQCMDS (Solves #311)
  - Fix CPL definition for LGDT (Solves #312)
  - Fix CPL definition for VMCALL (Solves #313)
  - Several bug fixes and improvements for the ENC2 library.
     For a list of unsupported IFORMS, please check the `enc2_unsupported_ref.json` file.
  - Fix build with the clang built of llvm-project trunk (Solves #315)

Modify:
  - Improve Python code quality
    (Solves #314)
    (Solves #317)

We express our gratitude to all members of the XED community for their valuable contributions.

Co-authored-by: marjevan <[email protected]>

External Release v2023.12.19

This release updates XED according to Intel APX (Rev-03) and Intel AVX10 (Rev-02) architecture specifications, December 2023.

General:
  - The XED user guide was updated with explanations for APX, AVX10, and more (https://intelxed.github.io/)
  - Updated Python version requirement and documentation to 3.8 (closes #306)

Added:
  - Added new APX promoted instructions: RAO-INT and USER-MSR (APX Arch Spec Rev-03)
  - Added a complete XED encoder support for Intel APX architecture
  - APX(CCMPcc/CTESTcc): Added operand parser API that extracts the default-flags-values from XED DFV pseudo-register
  - Updated APX CPUID sensitivity with additional Legacy/VEX CPUID records
  - FRED: Added compatibility mode SYSCALL

Fixed:
  - Fixed missing REX2 prefix restriction for several legacy instructions
  - APX/JMPABS: Added missing RIP suppressed operand
  - ENC2: Fixed the encoding of instruction's operands
  - Fixed CPUID records for KEYLOCKER and MOVDIR instructions

Modified:
  - Updated AVX10 CPUID sensitivity of 64-bit KMASK instructions (AVX10 Arch Spec Rev-02)
  - Improved Python code for genutil.py (resolves #307)

Co-authored-by: marjevan <[email protected]>

External Release v2023.10.11

Updated CPUs and instructions according to ISE (Intel® Architecture
Instruction Set Extensions and Future Features) rev-050, September 2023.

Added:
  - New USER_MSR and FRED instructions
  - New chips: Emerald Rapids, Clearwater Forest and Panther Lake
  - ENC2 updates with support for AMX/EVEX, IMM dest operand and EVEX
    scalable operand size instructions
  - Instructions for contributing to the Intel® XED project (README.md)

Fixed:
  - xed_agen() API: Avoid potential signed integer overflow (closes #305)
  - AMX: Fixed element types and updated extension definition

Modified:
  - Updated DAZ behavior of several AVX_NE_CONVERT instructions
  - Dropped Grand Ridge (No new ISA over SRF)
  - Updated PBNDKB CPUID name

Co-authored-by: marjevan <[email protected]>

External Release v2023.08.21 with APX and AVX10 support

External Release v2023.07.09

Added new CPUs and instructions according to ISE (Intel Architecture Instruction Set Extensions
and Future Features) rev-049, June 2023.

Added:
  - Added new chips: Arrow-Lake and Lunar-Lake
  - Added new instructions: AVX-VNNI-INT16, SHA512, SM3, SM4 and PBNDKB
  - Updated SRF with UINTR and ENQCMD support

External Release v2023.06.07

General:
  - Updated Python version requirement to 3.7

Fixed:
  - Re-enable XED root directory renaming (fixes #300)
  - Disassembler: Add CET "notrack" prefix emit (#278)

Improved:
  - Improve decoder code size
  - XED Examples: Improve Code Quality

External Release v2023.04.16

Updated CPUs and instructions according to ISE (Intel Architecture
Instruction Set Extensions and Future Features) rev-048, March 2023.

General:
  - Updated Python version requirement to 3.6 (closes #293)

Added:
  - Support new AMX instructions: TCMMIMFP16PS and TCMMRLFP16PS
  - Support Clang15 build
  - Support decode-encode of SAE/ROUNDC ignored ISA
  - Added mandatory 66 prefix API: `xed_operand_values_mandatory_66_prefix()`

Fixed:
  - Fixed XED-ILD standalone library for AVX512 instructions (fixes #298)
  - Chip-Check: Fixed CLDEMOTE mapping (for TREMONT and ALDER_LAKE)
  - Fixed Operand API: `xed_operand_values_print_short()`
  - Fixed FADD operand visibility
  - Changed NOP-0F1F to match SDM definition
  - Removed BROADCAST definition from VINSERTF128
  - Added missing UNDOCUMENTED attribute to instructions not documented in SDM
  - Fixed memory operand for PREFETCH instructions
  - Fixed SENDUIPI register operand width (fixes #292)
  - Fixed AMD LWP{INS,VAL} operand width (fixes #299)
  - Fixed git describe fail message (fixes #291)
  - Updated xed-doc-top (fixes #294)
  - Fixed libxed documentation for Windows (fixes #295)
  - Fixed legal headers

Modified:
  - Renamed XED operand: "REXRR" -> "REXR4"

External Release v2022.10.11

Updated CPUs and instructions according to ISE (Intel Architecture Instruction Set Extensions
and Future Features) rev-046, September 2022.

Added:
  - Added new chips: Granite Rapids, Sierra Forest, Grand Ridge and Lakefield
  - Added new Instructions: AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8, CMPCCXADD,
     ICACHE_PREFETCH, MSRLIST, RAO-INT and WRMSRNS
  - Added getter API for VEX.pp prefix encoding value

Fixed:
  - Fixed instructions-set list for SPR
  - Fixed first operand access definition for SSE compute instructions (#287)

Modified:
  - Internal core modifications and updates

External Release v2022.08.11

General:
- Drop KNC Support

Added:
- Support Clang14 static build (Resolves #283)

Modified:
- Examples: Improve encoding for non-vector 64bit GPR instructions
- Examples: Support repeatable "-set" knob for setting multiple operands (xed.c
and xed-ex1.c)

Fixed:
- Fixed decoder length check (ILD) for VEX instructions
- Fixed STACKPUSH, STACKPOP registers definition
- Fixed registers definition for the instructions: SWAPGS FXTRACT, F[,A]PTAN, and FSINCOS.
- Fixed lock documentation (#280)
- Improve EVEX Ubit handling and error detection