Intel® Compiler for SystemC* (ICSC) translates synthesizable SystemC design to synthesizable SystemVerilog design.

ICSC supports SystemC synthesizable subset in method and thread processes and arbitrary C++ code in module constructors. The tool produces human-readable SystemVerilog for complex multi-module designs in tens of seconds. This tool is focused on improving productivity of design and verification engineers and leaves optimization work for an underlying logic synthesis tool. It performs design checks to detect non-synthesizable code and common coding mistakes. ICSC is based on Clang/LLVM 15.0.7 and includes SystemC 3.0.0 RC.

ICSC generates SystemVerilog (IEEE 1800-2017) code. To convert SystemVerilog to Verilog (IEEE 1364-2005) there is SV2V tool which is compatible with ICSC.

ICSC is focused on productivity of design engineers with multiple features and advantages:

• C++11/14/17/20 support
• SystemC synthesizable standard support
• Arbitrary C++ at elaboration phase, including module constructors
• Human-readable generated Verilog code
• CMake based project, no pragmas or extra scripts required
• Fast translation procedure, seconds to a few minutes

Common SystemC Library consists of types, modules and functions which could be used in SystemC designs and testbench code. The main part of the library are communication channels including Target/Initiator, FIFO, Register and others. The channels have functional interfaces similar to TLM 1.0.

There are Communication channels training slides.

See more information at Common SystemC Library .

ICSC is based on Clang/LLVM frontend and can be installed at most Linux OS. There is install.sh script that downloads and builds ICSC and the required dependencies at SLES12, Ubuntu 22.04, and Ubuntu 20.04.

An instruction how to build and run ISCS at Ubuntu 20.04/22.04 is given at Getting started.

SystemC is C++ based language specified by IEEE 1666-2023.

SystemC is developed and supported by Accellera Systems Initiative.

The last available SystemC version is 3.0.0 RC available at SystemC Community Portal.

• SystemC-to-Verilog Compiler: a productivity-focused tool for hardware design in cycle-accurate SystemC at DvCon'2019: presentation, full paper
• Temporal assertions in SystemC at DvCon'2020 and SystemC evolution day'2020 presentation, full paper
• Intel Compiler for SystemC and SystemC common library at CHIPS tech summit 2022, presentation

Mikhail Moiseev mikhail.moiseev at intel.com