TMA 5.01 Fixes

[calebbiggers]

• Fixes brief descriptions ending in periods
• Fixes missing thresholds
• Fixes incorrect visibility for GRR file

[edwarddavidbaker]

Two metric thresholds on SKX and CLX look strange. Highlighted via create_perf_json.py failures. I assume it should be tma_code_stlb_hit > 5 but defer to Caleb regarding & p.

    {
        "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) ITLB was missed by instructions fetches, that later on hit in second-level TLB (STLB)",
        "MetricExpr": "max( 0 , tma_itlb_misses - tma_code_stlb_miss )",
        "MetricGroup": "FetchLat;MemoryTLB;TopdownL4;tma_L4_group;tma_itlb_misses_group",
        "MetricName": "tma_code_stlb_hit",
        "ScaleUnit": "100%",
        "MetricThreshold": "> 5 & p"
    },
    {
        "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by instruction fetches, performing a hardware page walk",
        "MetricExpr": "ITLB_MISSES.WALK_ACTIVE / tma_info_thread_clks",
        "MetricGroup": "FetchLat;MemoryTLB;TopdownL4;tma_L4_group;tma_itlb_misses_group",
        "MetricName": "tma_code_stlb_miss",
        "ScaleUnit": "100%",
        "MetricThreshold": "> 5 & p"
    },

[1perrytaylor]

Two metric thresholds on SKX and CLX look strange. Highlighted via create_perf_json.py failures. I assume it should be tma_code_stlb_hit > 5 but defer to Caleb regarding & p.

    {
        "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) ITLB was missed by instructions fetches, that later on hit in second-level TLB (STLB)",
        "MetricExpr": "max( 0 , tma_itlb_misses - tma_code_stlb_miss )",
        "MetricGroup": "FetchLat;MemoryTLB;TopdownL4;tma_L4_group;tma_itlb_misses_group",
        "MetricName": "tma_code_stlb_hit",
        "ScaleUnit": "100%",
        "MetricThreshold": "> 5 & p"
    },
    {
        "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by instruction fetches, performing a hardware page walk",
        "MetricExpr": "ITLB_MISSES.WALK_ACTIVE / tma_info_thread_clks",
        "MetricGroup": "FetchLat;MemoryTLB;TopdownL4;tma_L4_group;tma_itlb_misses_group",
        "MetricName": "tma_code_stlb_miss",
        "ScaleUnit": "100%",
        "MetricThreshold": "> 5 & p"
    },

Thanks Ed. We are working on an update.