NEC uCOM87AD microcontroller Verilog core for FPGA implementation. It was created using information from a datasheet, so its behavior may differ from the actual chip. © 2024 Sehyeon Kim(Raki)
- A near cycle-accurate, BSD2 licensed core.
- Emulates the CMOS version of the CPU.
The steps below show how to instantiate the IKA87AD module in Verilog:
- Download this repository or add it as a submodule to your project.
- You can use the Verilog snippet below to instantiate the module.
//Verilog module instantiation example
IKA87AD u_upd78c11 (
.i_EMUCLK ( ),
.i_MCUCLK_PCEN ( ),
.i_RESET_n ( ),
.i_STOP_n ( ),
.o_M1_n ( ),
.o_IO_n ( ),
.o_ALE ( ),
.o_RD_n ( ),
.o_WR_n ( ),
.o_ALE_OE ( ),
.o_RD_n_OE ( ),
.o_WR_n_OE ( ),
.o_A ( ),
.i_DI ( ),
.o_DO ( ),
.o_PD_DO_OE ( ),
.o_D_nA_SEL ( ),
.o_DO_OE ( ),
.o_REG_MM ( ),
.i_NMI_n ( ),
.i_INT1 ( ),
.i_INT2_n ( ),
.i_TI ( ),
.o_TO ( ),
.o_TO_PCEN ( ),
.o_TO_NCEN ( ),
.i_CI ( ),
.i_PA_I ( ),
.o_PA_O ( ),
.o_PA_OE ( ),
.i_PB_I ( ),
.o_PB_O ( ),
.o_PB_OE ( ),
.i_PC_I ( ),
.o_PC_O ( ),
.o_PC_OE ( ),
.o_REG_MCC ( )
.i_PD_I ( ),
.o_PD_O ( ),
.o_PD_OE ( ),
.i_PF_I ( ),
.o_PF_O ( ),
.o_PF_OE ( ),
.i_ANx_DIGITAL ( ),
.o_ANx_ANALOG_CH ( ),
.i_ANx_ANALOG_DATA ( ),
.o_ANx_ANALOG_RD_n ( )
);- Attach your signals to the port. The direction and the polarity of the signals are described in the port names. The section below explains what the signals mean.
i_EMUCLKis your system clock.i_MCUCLK_PCENis the clock enable(positive logic) for positive edge of the microcontroller master clock.i_RESET_nis the synchronous reset.i_STOP_nis the input for stopping the CPU core. See the datasheet for more information. To change the time it takes for the CPU to resume opcode fetch after being released from a stop state, change a parameter valueHARD_STOP_RELEASE_WAITinside the module.
o_M1_nindicates that the CPU is fetching an opcode. This is originally achieved by pulling the MODE1 pin to GND.o_IO_nindicates that the CPU is reading/writing data. This is originally achieved by pulling the MODE0 pin to GND.o_ALE,o_RD_n,o_WR_nare the asynchronous bus control signals.o_Ais the address output sourced by ther program counter.i_DIando_DOare the data input/output port, respectively.- The original chip uses the port D for address low and for data IO.
o_PD_DO_OEis the output enable of the multiplexed bus. o_D_nA_SELselects the output mode of the multiplexed bus.- You can still use the dedicated data buses instead of the multiplexed bus. In this case, you can use
o_DO_OEto control output drivers. o_REG_MMis the MM register output.
i_NMI_n,i_INT1,i_INT2_nare the interrupt inputs.
i_TI,o_TO,i_CIare ther timer/event counter related signals. See the datasheet for the details.o_TO_PCENando_TO_NCENis positive/negative clock enable of the TO output. These output make synchronized circuits easy.i_Px_I,o_Px_O,o_Px_OEare the GPIO ports. Note that the port D can only control bytewise direction.o_REG_MCCis the MCC register output.
i_ANx_DIGITALis the digital input port for the port AN7-4. They can perform negative edge detection.o_ANx_ANALOG_CHselects external ADCs.i_ANx_ANALOG_DATAgrabs data from the external ADCs.o_ANx_ANALOG_RD_nis the ADC read strobe. It samples data at the rising edge.
The original chip can change the memory map with the MODE1/0 pin and the MM register. Instead of implementing the original hardware, I added the o_A to output the current address of the program counter directly, to give the user flexibility. The entire 16-bit address space that the CPU core can access goes to the o_A port. It's up to you to decide how you want to arrange storage components.