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AES加密解密算法的Verilog实现

Verilog 58 28 Updated Jan 17, 2016

Generator for CRC HDL code (VHDL, Verilog, MyHDL)

Python 28 8 Updated Oct 13, 2023

SERV - The SErial RISC-V CPU

Verilog 1,411 186 Updated Oct 17, 2024

Xilinx Virtual Cable Daemon

C 110 61 Updated Feb 10, 2022

Xilinx Virtual Cable Server for Raspberry Pi

C 108 24 Updated Mar 14, 2022

ECP5 breakout board in a feather physical format

HTML 486 58 Updated May 7, 2024

Vim 中文文档计划

C 1,970 265 Updated Oct 13, 2023

Send video/audio over HDMI on an FPGA

SystemVerilog 1,083 112 Updated Feb 3, 2024

🐱 Run Clash Tunnel on Koolshare OpenWrt

ASP 1,333 241 Updated Jun 24, 2020

A Verilog HDL model of the MOS 6502 CPU

Verilog 326 93 Updated Apr 8, 2023
JavaScript 360 89 Updated May 18, 2018

LPCOpen library for NXP LPC43xx with Keil

C 8 10 Updated Jul 7, 2015

hexo blog

HTML 4 Updated Sep 9, 2019

iCESugar FPGA Board (base on iCE40UP5k)

Verilog 356 96 Updated Jun 5, 2024
C 2,306 974 Updated Aug 15, 2024

Standalone SDR experiment using multicore MCU - FM version

C 15 8 Updated Apr 14, 2018

CentSDR: tiny handheld standalone software defined receiver with LCD display.

C 105 49 Updated Jan 11, 2021