Risc-V core goes here, hopefully in a couple of years.

1. Implement ALU and CLU
2. Implement decoding
3. Implement RVFI
4. Simulate with Verilator or some custom Rust simulator yeeehaw!
5. Use Shake to build, synthesize and verilate
6. Pipeline!
7. Build cache hierarchy
8. Predict some branches
9. Synthesize! With Shake of course
10. cabal run clash --write-ghc-environment-files=always -- Core --verilog

• https://www.youtube.com/watch?v=NFguFKbuB_c
• https://github.com/christiaanb/contranomy/blob/tutorial/Tutorial.md

• https://unsafeperform.io/blog/2018-09-23-cpu_modeling_in_c_ash/

• https://github.com/gergoerdi/clash-intel8080

• https://riscv.org/technical/specifications/

• https://github.com/riscv/riscv-asm-manual/blob/master/riscv-asm.md

• https://hackage.haskell.org/package/clash-prelude-1.2.4/docs/Clash-Prelude.html

• https://github.com/SymbioticEDA/riscv-formal

• https://github.com/adamwalker/clash-riscv

• https://hackage.haskell.org/package/clash-prelude-1.2.4/docs/Clash-Prelude-BlockRam.html#usingrams

• https://gergo.erdi.hu/blog/2020-05-07-integrating_verilator_and_clash_via_cabal/