1. Write structural and dataflow Verilog HDL models for
a) 4-bit ripple carry adder.
b) 4-bit carry Adder – cum Subtractor.
c) 2-digit BCD adder / subtractor.
d) 4-bit carry look ahead adder
e) 4-bit comparator

2. Write a Verilog HDL program in behavioral model for
a) 8:1 multiplexer
b) 3:8 decoder
c) 8:3 encoder
d) 8 bit parity generator and checker

3. Write a Verilog HDL program in Hierarchical structural model for
a) 16:1 multiplexer realization using 4:1 multiplexer
b) 3:8 decoder realization through 2:4 decoder
c) 8-bit comparator using 4-bit comparators and additional logic

4. Write a Verilog HDL program in behavioral model for D,T and JK flip flops, shift registers and
   counters.

5. Write a Verilog HDL program in structural and behavioral models for
a) 8 bit asynchronous up-down counter b) 8 bit synchronous up-down counter

6. Write a Verilog HDL program for 4 bit sequence detector through Moore state machines

7. Write a Verilog HDL program for 4 bit sequence detector through Mealy state machines

1. Basic Logic Gates: Inverter, NAND and NOR
2. Half Adder and Full Adder
3. 2:1 Multiplexer and 4:1 Multiplexer using 2:1 Multiplexer
4. one bit comparator and four-bit magnitude comparator using one bit comparator
5. Implement the Layout of CMOS Inverter.
6. Implement the Layout of CMOS NAND.

1. A total of 10 experiments must be completed in the semester.
2. Minimum of 5 experiments from Part-A and 5 from Part-B is compulsory.