iMX.RT EHCI add dcache support and other fixes + refactor #2061
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- change CFG_TUH_ENDPOINT_MAX to 16 (max endpoint pair per device) if not defined - change QHD_MAX for EHCI, should be user configurable and more optimized in the future
…rsive hub removal with usbh queue
… and new setup complete in the same isr frame change usbd edpt busy/stalled/claimed value to 0/1 instead of (true/false) since they are 1-bit field.
- more dcache clean/invalidate - extract init_periodic_list() - improve isr list handling
HiFiPhile
reviewed
May 18, 2023
| @@ -50,6 +50,10 @@ | |||
| SCB_InvalidateDCache_by_Addr(addr, (int32_t) data_size); | |||
| } | |||
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| void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) { | |||
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How about make the cache related function optional (default ON) ?
For IMX.RT in order to have best performance, RAM will be configured to ITCM & DTCM, so they are accessed at CPU clock instead of bus clock (600MHz vs 133MHz)
Since TCM bypass the cache there is no need to flush or invalidate.
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ah you are right, I think we can check the address to see if it is within the DTCM (non-cachable) and skip the clean/invalidate will update in the next push or so. Circuitpython is currently placing ehci_data and/or user memory randomly and may not be in DTCM.
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DTCM is 1MB reserved in 2000000-2010000,this should be good enough.
hathach
changed the title
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Describe the PR
not defined
optimized in the future
** other minor usbd tweak **
(true/false) since they are 1-bit field.