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This repo is to collect the state-of-the-art GNN hardware acceleration paper
List of papers related to Vision Transformers quantization and hardware acceleration in recent AI conferences and journals.
Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators
The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference
CHARM: Composing Heterogeneous Accelerators on Versal ACAP Architecture
End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.
CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
research, experimentation and implementation of hardware-agnostic accelerated DL framework
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
C++ RTL simulator for EIE(https://arxiv.org/abs/1602.01528)
A curated list of awesome C++ (or C) frameworks, libraries, resources, and shiny things. Inspired by awesome-... stuff.
Open source version of ArchGym project.
Open deep learning compiler stack for cpu, gpu and specialized accelerators
DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator
Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM stan…
FPGA based Vision Transformer accelerator (Harvard CS205)
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Example code for Modern SystemC using Modern C++
Public repository for PySysC, (From SC Common Practices Subgroup)
A SystemC productivity library: https://minres.github.io/SystemC-Components/
Verilog AXI stream components for FPGA implementation
